ELF > @ @ , + GNU % PQrfanv UHSH 1HH HCf HC0H 1 HCfPHCfpH 1 HCfP HCpH 1 HCP(HCp$H 1 HCP*HC@p)H @1 HCfP,HC@p+H @1 HCP0HC@p.H @1 HCP8HCp4H 1 HCf HCfp1H uH 1 H[HCPXHCpTH 1 fffff. UH H fff. UHH H]LeLm L AA$ v;H H IT$fR>Et5fxf IL$fQ>HH H]LeLmf fyfIL$fQ>ff. UHH H]LeLm H L AH A$ u Eu>IT$R4IL$Q4IL$Q8HH H]LeLmf. IT$R4IL$Q4IL$Q8 UHH H]LeLm E1L H L uHSDj$A HL C
u 1EH]LeLm 1EH]LeLmfUHH H]LeLm L AHL Et-HSR(HKQ(LH H]LeLm HSR(HKQ(ffff. UHHH $Ld$ H IH A$ HH H $Ld$f UH o t f f UHAWAVAUATSH GHAtHG@$ txG tHCD`4EHCDp/AukHC@/DAd u# ItVXA HC@/DuC
tHC@4HCD`4HCD`8H[A\A]A^A_ ǃ HC DH Hp1 H3뺐UHH0H]LeLmLuL} HAL f{ xHC@4HS$?B4HSB8H{ H{0 E { H H v HP H L H` Hh Hǃ` Hǃh LeH]LmLuL} D L L H Iu'LL D H-HC H Hp1 H LH @ offff. UHSH HuHC@4 HSB4HSB8H[ @ UHSH ftC = = = = t= u 18 tY tSWu HO1҈Q)WtHWB)HWB)G
t f D XA H HuX[HWB)
닸 f UHAUATSH 9 HA HGH Ht C
HS1fB,E L 1ҹ A9 % ЃHSfB,HCf@,A uL @ XA HCf@,u2IuHC H Hp1 HH[A\A] HSfB,D H[A\A] 1҉A9rE D HCfP>fҸ < f D t 1҉A9rȁ ȃ! 1 1҉A9s
Ƀu% ȃ UHH H $Ld$Ll$Lt$ L H IL IM A|$ A4$HA|$ S At$HHCP(AD$ < < AL$
ЃE FHSfR>f HKA(AT$ πW DHSfB>HCf@>AT$
t/ m t Df HSfR,HKfQ,HSfB> Hǃ Ct
HLL H $Ld$Ll$Lt$f. Hcf D HS1B8Hf{ aHC@4HS B4HSB8E8 v c HSB(7 @ HSfR,HKfQ,HSB( Hǃ ~uf UHATS H vHCfP>F tu<tK1[A\ @ HCfP>| HCf@>tH 1 D HCf@,HKfA,HC@$ u_HCfP>| HCf@>t9HCf@,HSfB, HC@$% = 5HCD`)HCAD`) A HCD`)H 1 f UHAWAVAUATSH HH Lg H/HCf ҃ Z C HCDp@E1탻 vHCDhDC A @ 5 A ( @ % t HCH@HtHЅ uHC HC(HS(H H LƉ i@B u HCH@He HЉ D? u HCH@ H HЉ Ey i D% t IDŽ$0 A$< C
r HCH8 d H@HW HA$8 IDŽ$` C
@u IDŽ$` A t I$` f{ y I$` v I$` A I$` At I$` A t At I$` A t I$` A@t I$` D ɉD t D A ADH ADŽ$@ HCPHA A$@ A t) = A$@ ~ I$` A V A$@
I$` HH @ I$` H @ I$` ǃ fADŽ$l fADŽ$n ADŽ$t % A$h C
ADŽ$x A$x CL L HH L% % A$| HH L H 11Hǃ H v5H( H HP 11 Hp Hǃh { MD$1Iٹ H AuvHL IL$LH 1 Lk0C8 Hs0ID$HCH HCxI<$ Ai H{ H L L HD[A\A]A^A_ GL D t @ @ 8 f D he J D
A$8 A$< oI$` | H I$` D A$@ A$@
0 A$@ 2I$` !f D AWI$` F D D A$x fA$l o @ H5 H` H5 H` Hh H H f. D% ? /f. A$8 H A$@ I$` | @ A$8 f. C It$H 1A It$H 1 t H A It$H A L I uI H LEI$It$H HHH1 f{ iHC@4HS B4HSB8MIt$H 1 ADŽ$x Hh It$H 1 BIt$H A It$H 1 f= 9= ,H H 1 C f= = H H 1 f= = H H 1 CW H @I$` UHH H $Ld$Ll$Lt$ L HL H I L u1IDH EtsC H HHǃ Hǃ Hǃ LL H{ L H $Ld$Ll$Lt$ÐIFHt!D@EwH@ Ht x cCZw D Hǃ ; UHH H]LeLm L HL IHC@$ u
H u/LL H{ H H]LeLmHC H Hp1 HC H Hp1 H߾ H߾ H H H @ Hi UHHH $Ld$ HHIt5A$ H HHHt H HP H $Ld$þ_ H UHSH HtHGH@HtHC { 1Iٹ H L@ t
H[ HH{ uf{ y, vDD EtDH Eu fHSR4HKQ4HKQ8 wffff. UHSH f HxHG@4HW$?B4HWB8 v
D u.H{ u{ HމE EH[f H uHP u ߋuff. UHAWAVAUATSHh HuH H HEHx( A H H@HtDHMȃH9H DDHC@$DA
u*f. I
XA HC@$DuH5 H H' H HEH L`(
M AD$ AT$ʁ
H{ ;x = s L AL$D 1AMbAA$Aс C 1Ҹ } 19v> D 9, uHw1H HCP. t } S ID$8E1E9l$0t P 5
HA @ AD$% ɃMHC Lh L(M I H LLx H LH H H E1LDEH)ȹ H40ALI HC Lx H8H H H H@`H LЅ x B I|$8E|$0H}HC L(M M M E~$HE1H] @ H A9H]E1MDHuLAV \ Hh L` HEHx HUIL$8 E1LeIeH% H- EH]HEHEI^Efك
H}LcG % HE% IH}HG H Hm۶m۶mHH HHH HAFHHH H , H}LcHLMLx HUj MLxH}% HELA)HAEHEHAEHEHAEEAE AMAE AE !AEHEIHEHA]HAEHHAEHHA AEj DEeAE AE !AEHUILH+` H= LA HMID;\ VLeHAE AE AE AE AE AE AE AE AD$t f= yĀ= tH H 1 f= y= tH H 1 똾/ H p H 3 UHH`H]LeLmLuL} H IHx HLJ tM CS0Hs8% HG ɃH8H H H H@(HtE1DCEuaC CCHs H {t L LHs L H]LeLmLuL} C C% EHG Hp H8HF H H6 H@HtE1 ID$ H8HI$x H H H@HtE1M ID$ H8C HS0Lk8 H H H@PHt LMLk8E$\ E1M$h E eH% H- H]HEHEIU % H% IE HMHA H Hm۶m۶mHH HHAMH HHHH H L)HHc H}o H% ILA E;$\ I9H]Lk8ID$ H8HS0 H H} H@(HvE1MLDCEg I$ f D H $ @ Lk8fH @ H @ H w @ H ' = H HEHU HUHEf. UHSH H HH PtptZ 1HOHK HcLtDH HHCDD HD DtH f D HWRPH @ H t u%H Hx( t-Hǃ H[ D H@H Hx( u uH UHH H]LeLm L HL H IuLL H]LeLmHC H Hp1 HQH Ht@HH HtH @ H H UHAWAVAUATSH( L HL HCDp0AFE1E1w~ ) D% > EEA?A W EA: p EAA EAAi AAA LfffEt H[ 1H0 HP0H H(D[A\A]A^A_ @ HCDp0A tHCf@ă? H H A @H DPEf A0 A. AH : HSB0 H D HCDx0H H A tW@ H DX E @tHx( $ AEH8 A t@ H A ` uNA HC H Hp1 H @H HC HS@H H H zH X ZP EA A C t
x DDH DmDuLeHEHC@$D, C
H @s H H } P% HE% H 11IAIHf. H H} I$0 I$( H9HFH)HI$8 tM ID*AHtHH H @ A H LH} H}% X X DmDuLef= = H H 1 IL$Di A ,H H P% HE% H>E11IEIHf D HH} tiI$0 I$( H9HFH)HI$8 t2B IHHA It
HuHuIL$Dq E1E1Ht C @U H( ǃ@ 1ɺ _ f= u= hH H 1 H GHC DH Hp1 H f= = HC DH H HP1 HC H Hp1 HS B0f= = H H 1 H HC DH Hp1 HHCDp0if= = H H 1 HC DH Hp1 Hdffffff. UHAWAVAUATSH HHH { HH HH HCfP>ЃtW J HC@fP>HCP4HCP4!HS B4HSB8L01 LpHE HE LHE HE HH H( A eH% HIOH(Dž$( H IHGf 1L MHE HE HHE HE HE r HEDž0 Dž4 DžH5 DžL @p HDžX DžP LeH HCfP HCfH LHHǃ Hǃ Hf ff{ 2 @ HH HDžp HE HxHMHMH( LH @ HtIVHRu
H HuH(L { H @ ǃ@ HCfP>XA $f" "I@,M $ E1䋃 uD ߉ H Et DD EtDH EDDHC@4HS B4HSB8Hf ff{ fH f ff{ E1 H D[A\A]A^A_ D$E~"HS$fB>E1 H i H HP H H @ 1x | D DD H HP Ai H H 1 HCf@>$?HSfB>ApH 1A WUHH0H]LeLmLuL} L H IIL H I f{ L xHC@$ tN uEHC@$ tthI6H-LL H]LeLmLuL} @ H H @ uH f. LL L L L In H
h 3 = T a w 0 `
& @ M b P i % I u e ~
+ r \ ) x 2 w F g R g s { u u @ $ Z B ~ & C p N |
(
v
C R Y Z ` ( > @/ J a f v ` 0 6 k # g + 3 * { 8 | G { 0 0 0 7 H S d p o | ; @ D u u , 3 S ^ o x v J P P " P
r % P , 3 |
i " H - ~ 0 & E g 5 b 0 n z z ! I! T! ! t ! " ## h l# z # z t$ _& & Y' ^' ' ' ( h ( l %( l 4( h @( h L( h X( h d( h t( ( ( ( ( h ( h ( ( ) ) <) X G) o) t) ) ) ) ) ) ` ) ) ) ) ) ` ) * * * :* ?* m* Y, , , - t - "- - h - h - h - h - h . . :. 5/ U/ g/ / / / 0 $0 A0 0 } 1 2 v2 f 2 2 3 3 3 3 j4 u4 4 4 4 : 4 4 (
4 4 5 5 N5 5 y 6 6 #6 b 16 86 ?6 Y6 d6 x6 6 6 s 6 H 6 6 6 6 6 6 7
7 "7 -7 I7 V7 d7 } k7 r7 7 @ 7 7 7 7 8 9 v 9 9 (: r M: a: m i: u: : h; v ; v ; ; *< B< N< X
U< y<
< < < *= p= = = = = UH UH 1H H 1 1 @ sdhci_add_host sdhci_prepare_data sdhci_irq sdhci_cmd_irq sdhci_transfer_pio sdhci_read_block_pio sdhci_write_block_pio debug_quirks < `
P 0 8
@ 7 H <6>sdhci: Secure Digital Host Controller Interface driver
<6>sdhci: Copyright(c) Pierre Ossman
<7>sdhci: ============== REGISTER DUMP ==============
<7>sdhci: Sys addr: 0x%08x | Version: 0x%08x
<7>sdhci: Blk size: 0x%08x | Blk cnt: 0x%08x
<7>sdhci: Argument: 0x%08x | Trn mode: 0x%08x
<7>sdhci: Present: 0x%08x | Host ctl: 0x%08x
<7>sdhci: Power: 0x%08x | Blk gap: 0x%08x
<7>sdhci: Wake-up: 0x%08x | Clock: 0x%08x
<7>sdhci: Timeout: 0x%08x | Int stat: 0x%08x
<7>sdhci: Int enab: 0x%08x | Sig enab: 0x%08x
<7>sdhci: AC12 err: 0x%08x | Slot int: 0x%08x
<7>sdhci: Caps: 0x%08x | Caps_1: 0x%08x
<7>sdhci: Cmd: 0x%08x | Max curr: 0x%08x
<7>sdhci: ADMA Err: 0x%08x | ADMA Ptr: 0x%08x
<7>sdhci: ===========================================
<3>%s: Reset 0x%x never completed.
<3>%s: Controller removed during transfer!
<3>%s: Internal clock never stabilised.
<6>sdhci: Switching to 3.3V signalling voltage failed
<6>sdhci: Switching to 1.8V signalling voltage failed, retrying with S18R set to 0
<3>%s: Unknown controller version (%d). You may experience problems.
<4>%s: No suitable DMA available. Falling back to PIO.
<4>%s: Unable to allocate ADMA buffers. Falling back to standard DMA.
<3>%s: Hardware doesn't specify base clock frequency.
<3>%s: Hardware doesn't specify timeout clock frequency.
<3>%s: Hardware doesn't report any support voltages.
<4>%s: Invalid maximum block size, assuming 512 bytes
<6>%s: SDHCI controller on %s [%s] using %s
<7>sdhci:sdhci [%s()]: Controller doesn't have SDMA capability
<7>sdhci:sdhci [%s()]: Disabling DMA as it is marked broken
<7>sdhci:sdhci [%s()]: Disabling ADMA as it is marked broken
<3>%s: Card removed during transfer!
<3>%s: Controller never released inhibit bit(s).
<4>%s: Too large timeout requested!
<3>%s: Unsupported response type!
<7>sdhci:sdhci [%s()]: Reverting to PIO because of transfer size (%d)
<7>sdhci:sdhci [%s()]: Reverting to PIO because of bad alignment
<3>%s: Timeout waiting for hardware interrupt.
<3>%s: Got command interrupt 0x%08x even though no command operation was in progress.
<3>%s: Got data interrupt 0x%08x even though no data operation was in progress.
<3>%s: Card is consuming too much power!
<3>%s: Unexpected interrupt 0x%08x.
<7>sdhci:sdhci [%s()]: *** %s got interrupt: 0x%08x
<7>sdhci:sdhci [%s()]: Cannot wait for busy signal when also doing a data transfer <7>sdhci:sdhci [%s()]: PIO reading
<7>sdhci:sdhci [%s()]: PIO writing
<7>sdhci:sdhci [%s()]: PIO transfer complete.
<6>sdhci: Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock
<6>sdhci: Tuning procedure failed, falling back to fixed sampling clock
sdhci [%s()]: Disabling ADMA as it is marked broken
sdhci [%s()]: Disabling DMA as it is marked broken
sdhci [%s()]: Controller doesn't have SDMA capability
sdhci [%s()]: Reverting to PIO because of bad alignment
sdhci [%s()]: Reverting to PIO because of transfer size (%d)
sdhci [%s()]: *** %s got interrupt: 0x%08x
sdhci [%s()]: Cannot wait for busy signal when also doing a data transfer sdhci [%s()]: PIO transfer complete.
<7>sdhci: Host ctl2: 0x%08x
drivers/mmc/host/sdhci.c %s:: ADMA PIO DMA <3>%s: Resetting controller.
<3>%s: ADMA error
sdhci sdhci [%s()]: PIO reading
sdhci [%s()]: PIO writing
/ 1 2 Y= H @ 4 U ` ( ` ( ` $ ( ( ` 0 ) 4 ` < "* @ ` H &* L ` T - X ` ` ;/ d ` l 5 p ` x 5 | ` 6 ` . 0 / . 0 / . 0 / . 0 F! Q! ! 0 }, @ , P - ` 3 p 3 r4 5 5 } } } } 0 9 0 ^; 8 H w; P parm=debug_quirks:Force certain quirks. license=GPL description=Secure Digital Host Controller Interface core driver author=Pierre Ossman parmtype=debug_quirks:uint srcversion=0489C3E235C8238AFF0EB14 depends=mmc_core vermagic=2.6.32-358.el6.x86_64 SMP mod_unload modversions $ q ( " 0 8 1 @ H B P X T o s n ( sdhci_free_host sdhci_remove_host sdhci_add_host sdhci_alloc_host sdhci_resume_host sdhci_suspend_host 5 u ( 0 8 @ H P j X ` h p 8 x r }( J, e- ". 5 : @#R module_layout o< disable_irq 9O per_cpu__current_task q] mmc_detect_change c del_timer =u led_classdev_register R mmc_free_host '| autoremove_wake_function tM mmc_resume_host ˑ malloc_sizes =+ dynamic_debug_enabled2 s8 _spin_lock mmc_suspend_host ? sg_next __const_udelay &j init_timer_key *q _spin_lock_irqsave h} jiffies __init_waitqueue_head del_timer_sync sg_miter_start cs printk __tasklet_schedule G sg_miter_stop 9 mcount R0 warn_slowpath_null m per_cpu__kernel_stack yK _spin_unlock_irqrestore tasklet_init c EE mod_timer m request_threaded_irq +fP sg_miter_next K"y tasklet_kill NOvx pv_irq_ops G usleep_range ; msecs_to_jiffies param_get_uint ?, schedule_timeout dynamic_debug_enabled Q9 mmc_add_host .\ mmc_alloc_host 8|l& wake_up_process D kmem_cache_alloc_trace G) __phys_addr T.d __wake_up xcQD mmc_remove_host 81@ led_classdev_unregister enable_irq z kfree dl# memcpy /3 prepare_to_wait H̅2 param_set_uint "&˜ finish_wait o`u bad_dma_address ۞ snprintf 8¹ mmc_request_done ҁn dma_ops ث
free_irq ( ( ( ( ( ( ( M ( v ( ( * y P ( ( y 0 P 8 @ ` P y X P ` h x y ` y ` y s P y } y ( 0 @ y H P X h y p x sdhci | p H d module.sig F Q&
j@7 5| ϫzoֶ
:0 _A*~Hn9u ĜiYY
! " $ & ' $ ' 6 P f P s s ` G ' P < p `
G & P ' : ` - O @/ c & o 0 y " ( ( P " ( " P ( P " x ( ` " ( P* 0. & " ( 7 F " @ ( W f " ( w s
" h ( " ( } 7 < 0 ( ( @ A ( ( 9 T ( i
$ = " V o 0 1 @ B P 1 T N ( k q } # 0 ` ; $ 0 2 }B H W f v (
$ & 3 I Z i z 7 V. 4 J ] d r p
'-3 8 I T k } p i
s
,
sdhci.c sdhci_drv_exit sdhci_drv_init sdhci_dumpregs sdhci_enable_preset_value sdhci_enable_sdio_irq sdhci_get_ro sdhci_led_control sdhci_tuning_timer tasklet_schedule sdhci_reset sdhci_init sdhci_set_power sdhci_set_clock sdhci_set_ios sdhci_start_signal_voltage_switch debug_quirks sdhci_ops sdhci_tasklet_card sdhci_tasklet_finish sdhci_timeout_timer __key.32374 sdhci_irq descriptor.32364 __func__.32361 descriptor.32367 descriptor.32360 sdhci_send_command descriptor.31083 __func__.31074 descriptor.31073 sdhci_finish_data sdhci_finish_command descriptor.30762 __func__.30763 descriptor.30621 __func__.30622 descriptor.32203 __func__.32204 descriptor.30689 __func__.30690 descriptor.32067 __func__.32068 sdhci_execute_tuning sdhci_request __mod_debug_quirks2644 __mod_license2642 __mod_description2641 __mod_author2640 __mod_debug_quirkstype2638 __param_debug_quirks __param_str_debug_quirks __ksymtab_sdhci_free_host __kstrtab_sdhci_free_host __kcrctab_sdhci_free_host __ksymtab_sdhci_remove_host __kstrtab_sdhci_remove_host __kcrctab_sdhci_remove_host __ksymtab_sdhci_add_host __kstrtab_sdhci_add_host __kcrctab_sdhci_add_host __ksymtab_sdhci_alloc_host __kstrtab_sdhci_alloc_host __kcrctab_sdhci_alloc_host __ksymtab_sdhci_resume_host __kstrtab_sdhci_resume_host __kcrctab_sdhci_resume_host __ksymtab_sdhci_suspend_host __kstrtab_sdhci_suspend_host __kcrctab_sdhci_suspend_host .LC19 sdhci.mod.c _rheldata __mod_srcversion86 __module_depends ____versions __mod_vermagic5 free_irq dma_ops mmc_request_done __this_module snprintf bad_dma_address finish_wait __crc_sdhci_add_host __crc_sdhci_free_host cleanup_module param_set_uint prepare_to_wait __crc_sdhci_remove_host memcpy kfree enable_irq led_classdev_unregister mmc_remove_host __wake_up __phys_addr kmem_cache_alloc_trace init_module wake_up_process mmc_alloc_host mmc_add_host dynamic_debug_enabled schedule_timeout param_get_uint msecs_to_jiffies usleep_range pv_irq_ops __crc_sdhci_suspend_host sdhci_suspend_host tasklet_kill __crc_sdhci_alloc_host sg_miter_next request_threaded_irq mod_timer tasklet_init _spin_unlock_irqrestore per_cpu__kernel_stack warn_slowpath_null mcount sg_miter_stop __tasklet_schedule printk sg_miter_start del_timer_sync __init_waitqueue_head sdhci_free_host jiffies sdhci_add_host _spin_lock_irqsave init_timer_key __const_udelay sg_next __crc_sdhci_resume_host mmc_suspend_host _spin_lock dynamic_debug_enabled2 sdhci_resume_host malloc_sizes mmc_resume_host sdhci_alloc_host autoremove_wake_function mmc_free_host led_classdev_register del_timer mmc_detect_change sdhci_remove_host per_cpu__current_task disable_irq sdhci.ko.debug rT .rodata.str1.1 .rodata.str1.8 .data .rheldata .rela.rodata .symtab .strtab .shstrtab .rela__mcount_loc .note.gnu.build-id .rela__bug_table .rela.gnu.linkonce.this_module .rela__verbose .note.module.sig .gnu_debuglink .rela__kcrctab_gpl .rela__ksymtab_gpl .rela__param .modinfo __ksymtab_strings .rela.smp_locks __versions .rela.parainstructions .rela.altinstructions .bss .altinstr_replacement .rela.text .rela.init.text .rela.exit.text h @ $ p = 0> ! ( 0_ @_ ( X_ $ _ ` ( u _ 4 ` / ` ( 2 a 2 n - Po ( ( xo x (
o { p @ ( H r C ps ( _ xt \ Z t (
u @w ( hw ` ( w ` 0x ( Py 0 y ( z g [ xz V X{ ( % } 8 ~ ( " 0 0 ( $ p @ @ ` < h ) g D 8
@ L T