f UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UH H H UHSHH t H[ @ A A H H H$ uE1A H H H$ uE1A H H H$ aE1A H H H$ .E1A H H H$ f UHSHH t H[ @ A A H H H$ uE1A H H H$ uE1A H H H$ aE1A H H H$ .E1A H H H$ f UHSHH t H[ @ A A H H H$ uE1A H H H$ uE1A H H H$ dffffff. UHSHH t H[ @ E1A H H H$ uHE1A H H $ H[ffffff. UHSHH t H[ @ A A H H H$ uE1A H H H$ uE1A H H H$ dffffff. UHSHH t H[ @ E1A H H H$ uE1A H H H$ uE1A H H H$ dE1A ( H H H$ 1E1A , H H H$ fff. UHSHH t H[ @ E1A H H H$ uE1A H H H$ uE1A H H H$ dE1A ( H H H$ 4ffffff. UHSHH t H[ @ E1A H H H$ uE1A H H H$ uE1A H H H$ dE1A ( H H H$ 4ffffff. UHSHH t H[ @ E1A H H H$ uE1A H H H$ uE1A H H H$ dE1A ( H H H$ 4ffffff. UHSHH t H[ @ E1A H H H$ uE1A H H H$ uE1A H H H$ dE1A H H H$ 1E1A $ H H H$ fff. UHSHH t H[ @ E1A H H H$ uE1A H H H$ uE1A H H H$ gfUHSHH t H[ @ E1A H H H$ uE1A H H H$ uE1A H H H$ gfUHSHH t H[ @ E1A H H H$ uE1A H H H$ uE1A H H H$ gfUHSHH t H[ @ E1A H H H$ uE1A H H H$ uE1A H H H$ dE1A H H H$ 4ffffff. UHSHH u+E1A H H H$ H[f UHSHH t H[ @ E1A H H H$ uE1A H H H$ uE1A H H H$ dE1A H H H$ 4ffffff. UHSHH u+E1A H H H$ H[f UHSHH t H[ @ E1A H H H$ uHE1A H H $ H[ffffff. UHSHH t H[ @ E1A H H H$ uE1A H H H$ uE1A H H H$ dE1A H H H$ 4ffffff. UHSHH t H[ @ E1A H H H$ uE1A H H H$ uE1A H H H$ dE1A H H H$ 4ffffff. UHSHH t H[ @ E1A H H H$ uE1A H H H$ uE1A H H H$ dE1A H H H$ 4ffffff. UHSHH t H[ @ E1A H H H$ uE1A H H H$ uE1A H H H$ gfUHSHH t H[ @ E1A H H H$ uE1A H H H$ uE1A H H H$ dE1A H H H$ 4ffffff. UHSHH t H[ @ E1A H H H$ uE1A H H H$ uE1A H H H$ gfUHSHH t H[ @ A A H H H$ uHE1A H H $ H[fff. UHSHH t H[ @ A A H H H$ uHE1A H H $ H[fff. UHSHH u+E1A H H H$ H[f UHSHH t H[ @ E1A H H H$ uHE1A H H $ H[ffffff. UHSHH t H[ @ E1A H H H$ uE1A H H H$ uE1A H H H$ gfUHSHH t H[ @ E1A H H H$ uE1A H H H$ uE1A H H H$ dE1A H H H$ 4ffffff. UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UH H ¸t H 1H UHH0H]LeHLmLu% Iŋ5 H}eH% DDL E HItOH LH P X Pp Ph Pl P H}H tH]LeLmLu H}DLL fff. UHHPLeLmIL}H]ALuA% HE5 H}eH% DHM A HIt5H A$ DhLDxH P H}H tH]LeLmLuL} HUH}ȉL fff. UHH0H]LeHLmLu% Iŋ5 H}eH% DDL E HIt0H HXH LH PH}H tH]LeLmLu H}DLL fff. UHHPLeLmIL}H]ILuA% HE5 H}eH% DHM A HIt7H I$LH HR8LhDxP H}H tH]LeLmLuL}ÐHUH}ȉL fff. UHH@H]LmHLeLuAL}% INj5 H}eH% DDL0 E HItEH HSHLH HPHSPHPHS0HP HS8Dh,P(H}H t H]LeLmLuL} H}DLL fff. UHH0H]LeHLmLu% Iŋ5 H}eH% DDL0 E HItAH HSHLH HPHSPHPHS0HP HS8P(H}H tH]LeLmLuf D H}DLL fff. UHH`H]LeHL}LmILuUILE% HEwHH}eH% DDHM0 E HItMH LxUHL` PM HHN$"HHL!HHH(H}L t H]LeLmLuL}f D HUH}DL ff. UIHщHH H UIHщHH H UIHщHH H UHHPH]LmHL}LeALuA% HE5 H}eH% DDHM E HItDHAA HXD LHH DhD Dx H} tH]LeLmLuL} HUH}DL ff. UHHPLeLmIL}H]ALuA% HE5 H}eH% DHM A HIt.H L`DhLDx H}HH t H]LeLmLuL}f. HUH}ȉL fff. UHHPLeLmIL}H]ALuA% HE5 H}eH% DHM A HIt.H L`DhLDx H}HH t H]LeLmLuL}f. HUH}ȉL fff. UHHPLeLmIL}H]ALuMA% HE5 H}eH% DHM A HIt5H L`DhLDx UH P H}H tH]LeLmLuL}HUH}ȉL fff. UHH@H]LmHLeLuIL}% INjwHH}eH% DDL E HIt"H LhH}LHH tH]LeLmLuL} D H}DLL @ UHH H=ff. UHH H ff. UHHPLeLmIL}H]ALuMA% HE5 H}eH% DHM A HIt:H IT$8LH DhDxP UPH}H tH]LeLmLuL} HUH}ȉL @ UHH0LeH]ILmLu% Iŋ5 H}eH% DL A HIt,H IT$8LH P H}H tH]LeLmLu @ H}؉LL D UHH0H]LeHLmLu% Iŋ5 H}eH% DDL E HIt6H H LH HR8HXP H}H tH]LeLmLuÐH}DLL fff. UHHPH]LeHL}LmILuI% HE5 H}eH% DDHM E HItNH HSHR8P SPIWRP1MtAT$ PH}LHH t H]LeLmLuL}f HUH}DL ff. UHHPH]LmHL}LeALuA% HE5 H}eH% DDHM E HItEH HSLH HRHR8P HSRDhDxPH}H tH]LeLmLuL}fHUH}DL ff. UHH@H]LeHLmLuIL}% INjwHH}eH% DDL E HIt@H HthHSHJHI8 H RPS PH}LHL t H]LeLmLuL} H}DLL @ HSHR8P SP1f UHH Hff. UHH Hff. UHH Hff. UHH Hff. UHH@H]LeHLmLuL}% Iŋ5 H}eH% DDL E HItIH IHC1HH@8 AG CAG AGH}LLH t H]LeLmLuL}f D H}DLL fff. UHH0H]LeHLmLu% Iŋ5 H}eH% DDL E HItRH HttHSHJHI8 H JHK HHRLH R`H@H} tH]LeLmLu D H}DLL @ HS1HR8P SP1ffffff. UHH@LeLmAH]LuIL}% INj5 H}eH% DL A HIt*H D` LhLH}HH tH]LeLmLuL} H}ȉLL ffff. UHH@LeLmAH]LuIL}% INj5 H}eH% DL A HIt*H D` LhLH}HH tH]LeLmLuL} H}ȉLL ffff. UHH0LeH]ALmLu% Iŋ5 H}eH% DL A HIt&H D` H}LHH tH]LeLmLufH}؉LL ffff. UHH@H]LeHLmLuIL}% INjwHH}eH% DDL E HIt3H L`I$ LHHR8PH}H tH]LeLmLuL} @ H}DLL @ UHH H-ff. UHH H
ff. UHH@H]LeHLmLuIL}% INjwHH}eH% DDL E HIt:H HXHSHLLHPHSHHR8P H}H tH]LeLmLuL} D H}DLL fff. UHH H ff. UHH Hff. UHH@H]LeHLmLuIL}% INj5 H}eH% DDL( E HItBH SL`LH P IT$HHPHSHR8P H}H t H]LeLmLuL}f. H}DLL fff. UHH@H]LeHLmLuL}% Iŋ5 H}eH% DDL E HItcH INj AG H; HG PhHAG AGh LLH AGl AG H} tH]LeLmLuL} @ H}DLL @ UHH`H]LeHLmLuIL}H}HU% HHEeH% DD DhHM5 H}EIcH0 HIt`DH,U UIHމP(HM,L`I| HHHMID IE H}LLH tH]LeLmLuL} @ HUH}DL ff. UHHpLmL}EH]LeALuH}uHUDE% HE5 I eH% DHMA H}A( !EDE HEи( DE HIt}H D`$HHEA DH HCED{ CEE|! HDA(D{ HEJ<#L@1 H}LHH tH]LeLmLuL} @ MHULH} U1 HH LeL HLmLuILH]L}HIHEHEHH HE HE H@HeeH % D A % H% e% GH H HEH HcH HC HH fIEH@8 C AECHHB@C1MtAF C= MA Hٺ 1 D H% H]LeLmLuL} @ UHw D UHH`H]LeHLmLuL}u% HE5 H}eH% DDHM E HItdH HI LsIFH@8 AD$ AFAD$C AD$EAD$I tvH}LLH t H]LeLmLuL}f D HUH}DL HCE1H@8 AD$ CAD$1z LA xHtH M Mt I@H@@`tH L I 4H H H 1LE LEffffff. U1 HH LmL LuAL}H]LLeIHHEHEHH HE HE H@HeeL$% A$D % I% e% A$GH L% LEMtmHcLL$ ID$ LL Et$ MM|$A L 1fA$= LL% H]LeLmLuL}ÐUH D U1 HH LmL LuAL}H]LLeIHHEHEHH HE HE H@HeeL$% A$D % I% e% A$GH L% LEMtmHcLL$ ID$ LL Et$ MM|$A L 1fA$= LL% H]LeLmLuL}ÐUH D U1 HH LeL LmIH]LuLL}HHEHEHH HE HE H@HeeL4% AD A % H% e% AGH HD H HH HC HH Mf~ MuIFH@8 C AFCAE C{I tl= MA Hٺ 1 D H% H]LeLmLuL}fIEE1H@8 C AEC1 D LA tMtL M Mt I@H@@`tH L M BH H H 1L Lffff. UH D U1 HH LmL LuIL}H]LLeHAHEHEHH HE HE H@HeeL$% A$D % I% e% A$GH L% LEM HcLL$ ID$ LL MA L 1fA$IFH@H@8 AD$ IF@E|$AD$A|$= LL% H]LeLmLuL}fUHw D U1 HH LmL LuIH]LeLL}HHEHEHH HE HE H@HeeL$% A$D % I% e% A$GH L% LEMt~HcLL$ ID$ L 1LfA$IFH@8 AD$ AFAD$A AD$= MA L 1 L% H]LeLmLuL} UH D U1 HH LmL LuIH]LeLL}HHEHEHH HE HE H@HeeL$% A$D % I% e% A$GH L% LEM HcLL$ ID$ L MfA$| IFHPHR8AT$ PAT$AV AT$H@MA L @`AD$= 1 L% H]LeLmLuL} IF1H@8 AD$ AFAD$1f. UHW D U1 HH LmL LuAH]LeLL}HHEHEHH HE HE H@HeeL$% A$D % I% e% A$GH L% LEMtZHcLL$ ID$ L Et$ MA L 1fA$= L% H]LeLmLuL} UH D U1HH LuL LeL}IIL H]LmHH L HEHEHH HE HE H@HeeH % D A % I% e% GH H HEH HcLH HC, HL AD$HMA4 1fH HK L{ { HHHN<8HL!HHS(A|$H D LL% H]LeLmLuL}fffff. UIHщHH HE UIHщHH H% UIHщHH H U1 HH LmL LuIL}H]LLeIHHEHEHH HE HE H@HeeL$% A$D % I% e% A$GH L% LEMtdHcLL$ ID$ LL AFHM|$MA L 1fA$A~H LL% H]LeLmLuL}f. UHH Hff. UHH H}ff. U1 HH LeL LuILmH]LL}IHHEHEHH HE HE H@HeeH % D A % H% e% GH H HEHtvHcH HC HH AFHMftiIEHPHR8S @CAE CA~HMA Hٺ 1 D H% H]LeLmLuL} IEH@8 C AEC1 UHH Hmff. UHH HMff. UHH H-ff. UHH H
ff. U1 HH LeL LmILuH]LL}IHHEHEHH HE HE H@HeeH % D A % I% e% GH H HEHtqHcLH HC HL AEHLsMA$ Hٺ 1fI H@8 CA}H D LL% H]LeLmLuL}UHH Hff. UHH H}ff. U1 HH LeL LuILmH]LL}IHHEHEHH HE HE H@HeeH % D A % I% e% GH H HEHtyHcLH HC HL AFHLkMA$ Hٺ 1fIEHHCIEH H@8 C A~H D LL% H]LeLmLuL} UHH Hff. UHH Hmff. U1 HH LeL LmILuH]LL}IHHEHEHH HE HE H@HeeH % D A % I% e% GH H HEH HcLH HC$ HL MA, Hٺ 1fAELsC IFHHCIEH@8 C = D LL% H]LeLmLuL}fff. UH D U1 HH LuL LmIH]LeLL}HHEHEHH HE HE H@HeeL$% A$D % I% e% A$GH L% LEM HcLL$ ID$ L fA$A AD$ I} A HG PhLAD$ AD$Ah MA$ L 1AD$Al AD$ = L% H]LeLmLuL}UHw D U1 HH LuL LmIH]LeLL}HHEHEHH HE HE H@HeeL$% A$D % I% e% A$GH L% LEM HcLL$ ID$ L MA$ L 1fA$A AD$ AX AD$Ap AD$Ah AD$Al AD$ = L% H]LeLmLuL}fff. UHw D U1 HH LmL LuIL}H]LLeHAHEHEHH HE HE H@HeeL$% A$D % I% e% A$GH L% LEMtHcLL$ ID$ LL MA L 1fA$A E|$AD$ A|$= LL% H]LeLmLuL}f UH D U1 HH LmL LuIH]LeLL}HHEHEHH HE HE H@HeeL$% A$D % I% e% A$GH L% LEMtfHcLL$ ID$ L Mt$MA$ L 1fA$I AD$= L% H]LeLmLuL}ff. UH D U1 HH LmL LuIL}H]LLeHIHEHEHH HE HE H@HeeL$% A$D % I% e% A$GH L% LEM HcLL$ ID$ LL MA$ L 1fA$IH@8 M|$AD$ A|$= LL% H]LeLmLuL} UH D U1 HH LmL LuIL}H]LLeAHHEHEHH HE HE H@HeeL$% A$D % I% e% A$GH L% LEM HcLL$ ID$, LL MA4 L 1fA$IFHID$IFPID$IF0ID$ IF8E|$,AD$(= LL% H]LeLmLuL}fffff. UHw D U1 HH LmL LuIH]LeLL}HHEHEHH HE HE H@HeeL$% A$D % I% e% A$GH L% LEMtyHcLL$ ID$, L MA4 L 1fA$IFHID$IFPID$IF0ID$ IF8AD$(= L% H]LeLmLuL} UH D U1HH L}L LmHI LLuH]LeHIHHEHEHH HE HE H@HeeH % DL D` uƃ H[f UH HGh ff. UH HGh ff. UHGHH@(@- H A `HH xH BHc @= JH DBHc A BMcB = L JH BHc = JHD BHc z= O H BHc = JH BHc = O JH BHc = JH BHcɁ = @ u~s HsE s s Hs s 1s Hs s 1s Hs K S$!ʉS EH]LeLmLu @ IH, @$@$M9Effff. UHHH $Ld$ HH Ht?H L Mt ID$@`t%H L Hǃ H $Ld$þ H fffff. UHHH $Ld$ H uH $Ld$ HCHL`( s LƜ A$ tDH HtHH H{ H{x tHCx HH $Ld$H H i H 1 ff. UHAWAVAUATSH HP LfIHF CH@I|` HCH@(x* C HCH@(x* HH H p L HI @ H H= ID IMHHCHHEH@(HM0 L A L ID$@` H L CH@IDh CH@ID` H D[A\A]A^A_f D H H L A
I$h I$ A$p H Ht A$ I$x , @ H I$x H A$ HB H
~H H Hm۶m۶m )HHcHHHHH HH)HHHH)HH H HHJ HBLJLB HzHrHHJ(LRLZ HHJ,HHJ0HHJ4HHJ8HHJH M H 1HM HMf @ UHAWAVAUATSH( HGw IHX(Ơ H Ep EUD:eGIH E1UHHE E @ D8e AAv ADHf@D< D(D AA7p Av Aź HA7t AAuAt fE L @ A ^DLk<]D8eM IFH@(@- x* DeE HEf ff} EAv H߹ Ơ EfR(ЉAp H([A\A]A^A_H H 1 !H H xHPAFt >AA/ H H 1 f L H H xH H * H 1 ff. UHAWAVAUATSH eL4% HuLo(A 1I? LcMiH K= tOC= HUH@HHP`LxhHt.HHU HUt:H H 1 AuH[A\A]A^A_ H H H Hx ) H Hx p H0@ p 41~H )HcH HHHm۶m۶mHHHH HH)Hm۶m۶mHHH H HHPH AF An AG AG Hh 1H ǂ Hx 4HHHx !H 1H < H H I$ H I$ cUHAWAVAUATSHX HuHG HIHEHHUH@(HEBH@HHG0H@hHEHF( @MtN tFtB U1H H HX[A\A]A^A_ÐU HUE M9Jtt E@ i I}8AH}LwHANL AH9 1LmIDA% @ A uPA I I9L tWMwHAX tHEHULHp (A t1L A f. DLLm@tH}LwA > ҃>A AƆ HEH H9E HMAUI}8q HMIu D= EuMe8Er LH߉E L EHX[A\A]A^A_fHUH H9UF \ HX[A\A]A^A_HEU9PtSI}8 HM1q Hq HE p p Hp HU r r Hr HMq q }Hq } HEP H@$!ЉA UHEPt %1H H $ 1H H L= M~IIEDLIEHuMe8X1H H UHAWAVAUATSH H_(IHǃ ǃ L ǃ ǃ ǃt HW(B-tǃt HW(z* H H Hǃ Hǃ HBH ID$(@- u
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L EDE I] zs HsE C DI]s Hs C DI]s Hs C 1I]s Hs C IUJ$!J Ef UHH@H]LeLmLuL} LwI HAAA E tH]LeLmLuL}ÐIF 0Pp HpHE HE @ IFp HpHE HE @ IFp HpHE HE@ IF}̋p HpHE HEﾭރ@ IFp HpHE HE1@ IFp HpHE HE@ IFP$!P A H I^ s HsE C DI^D s Hs C C|,I^s Hs C 1I^s Hs C IVJ$!J E| A g H R PLܮ LϮA L 贮uL詮 L蜮DL葮 L脮1LzIFP$!P De @ UHAVAUATS H_(IHǃ ǃ ǃ HG(@*<2 < Hǃ Hǃ Hǃ HG(x* Hǃ Hǃ Lǃ Hǃ Hǃ M D Hǃ ID$(@- Hǃ Hǃ Hǃ ID$(@$f=w5 f=b% H LH~AuID$(x*v H A[A\A]DA^ D Hǃ HW(H z*H Hǃ Hǃ HGH HG(x* Hǃ Hǃ ǃ D P*
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eL4% p8Hx H LlHuTH I9 AD % H\t M$ L b A$ L¾ b AL1Ҿ b A$ H 1ɺ p8Hx [A\A]1A^ Qf f H[A\A]A^fHt?ffffff. UHH@H]LeLmLuL} Lw(HvIt&ADH]LeLmLuL} KuӋtI`HUL AHUuHzp3 H= Iws t7AX % CAG,LC AG(C ]C ܿ HUA HUa/LE UH f9tH t @ fffff. UHH0H]LeLmLuL} L.H_(ILH=X# t'ADH]LeLmLuL} K*f tAX# HA At A At1f. H 땺 X# HE1 ID$ٺ \# HE1 Aź X# H AǾ\# H A9tAt AA AI EE1M Ml$ff D UH HH@(P*t@-t p t
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HSx\ t6HTH H9y/ H H9x HCx\ uH[ D HCx\ tH 1 H[ D UHH0H]LeLmLuL} HAAA AJ LHH)D E J LHH)HH@ ǀ D@ Dz {*X ǀT B B C- J LHH)DŽP J L1HH)L4H H I I 1E Idž D A@ J II)N$#I$ A$T HAxH]LeLmLuL}f. C*<t0<t,<t(J LHH)DŽP f D J LHH)DŽP f D ǀT B B H H ( H 1 =H H K H A@ H H - H 1 fff. UHATS HH?H;H IċC t4C uHK H H;LH [A\H H H C C D UHH H]LeLm HIL L LkxI] HL HLeH]Lmf UHH H]LeLm HIL L LkxA] HL LeH]Lmf. UHH H]LeLm HIL %L LkxfA] HL LeH]Lmf UHH H]LeLm HIL L LkxA] HL LeH]Lmf. UHH H $Ld$Ll$Lt$ HIIL [L LkxMu LH H $Ld$Ll$Lt$ff. UHH H $Ld$Ll$Lt$ HIAL L LkxEu LH H $Ld$Ll$Lt$ff. UHH H $Ld$Ll$Lt$ HIAL {L LkxfEu LH H $Ld$Ll$Lt$f. UHH H $Ld$Ll$Lt$ HIAL L LkxEu LH H $Ld$Ll$Lt$ff. UHH0H]LeLmLu HIIL L I Hu*1LcxM4$u7L H]LeLmLufI HHE HuHHu Hu UHH0H]LeLmLu HIAL L I Hu*1LcxE4$u7L H]LeLmLufI HHEkHuHHuiHu UHH0H]LeLmLu HIAL ^L I Hu*1LcxfE4$u6L H]LeLmLuÐI HHEHuHHuHu UHH0H]LeLmLu HIAL L I Hu*1LcxE4$u7L H]LeLmLufI HHE+HuHHu)Hu UHH H $Ld$Ll$Lt$ H HAt1p u=L L DIHLL H $Ld$Ll$Lt$H H H 1 UHH0LeLmAH]LuI H 11A A DD!t W tWA!ăt H HH)I @ Et
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ς ֎ ʌ intel_get_cxsr_latency i830_get_fifo_size i845_get_fifo_size _ ? i845_update_wm intel_calculate_wm i9xx_get_fifo_size ? @ _ ? @ ? i9xx_update_wm i965_update_wm g4x_update_wm g4x_check_srwm ?
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@ @ ? @ pineview_update_wm vlv_update_wm vlv_pipe_set_fifo_size gen6_check_mch_setup ilk_validate_wm_level skl_wm_flush_pipe ironlake_enable_drps sanitize_rc6_option cherryview_init_gt_powersave cherryview_setup_pctx valleyview_init_gt_powersave valleyview_setup_pctx 5-o *&_ &hb 5k *k \ironlake_set_drps Q Q R vlv_wm_get_hw_state vlv_get_fifo_size intel_set_memory_cxsr _ Z U U K < > 2 ' chv_phy_control_init vlv_cmnlane_wa chv_dpio_cmn_power_well_disable chv_dpio_cmn_power_well_enable skl_set_power_well skl_disable_dc6 skl_enable_dc6 gen9_enable_dc5 hsw_set_power_well sanitize_disable_power_well_option intel_power_well_disable intel_power_well_enable chv_phy_powergate_lanes chv_phy_powergate_ch bxt_disable_dc9 bxt_enable_dc9 p q
/ 2 3 i915_displayport_test_active_write display_crc_ctl_write display_crc_ctl_parse display_crc_ctl_tokenize pipe_crc_set_source i915_error_state_write i915_drop_caches_set i915_ring_test_irq_set i915_ring_stop_set i915_cache_sharing_set i915_min_freq_set i915_max_freq_set i915_parse_cmds copy_batch vmap_batch check_cmd " " # # # # # # # # # $# (# ,# 0# 4# 8# <# @# D# H# L# P# T# `# $ $ $ $ $ 0$ 4$ 8$ <$ @$ % % % R R R R R R R R @R DR HR LR PR TR XR \R R R R R $ 8 P@ P@ h h h " gen7_blt_get_cmd_length_mask gen7_bsd_get_cmd_length_mask gen7_render_get_cmd_length_mask ! @ @
? @ @ ? @ h i p q q y z ? ? 9x :x Cx Dx Ex Fx Gx @ ? ? @ h
@ ? ? P ? P ? ? ? @ ? ? @ i915_gem_context_destroy_ioctl i915_gem_context_create_ioctl i915_gem_create_context do_switch i915_gem_context_init i915_gem_execbuffer2 i915_gem_do_execbuffer i915_gem_check_execbuffer i915_gem_validate_context eb_lookup_vmas i915_gem_execbuffer_relocate_entry i915_gem_execbuffer i915_gem_ringbuffer_submission i915_reset_gen7_sol_offsets i915_gem_gtt_init sanitize_enable_ppgtt intel_rotate_fb_obj_pages snb_pte_encode ivb_pte_encode i915_gem_setup_global_gtt gen6_ppgtt_init gen6_ppgtt_allocate_page_directories i915_check_and_clear_faults i915_ppgtt_init_hw i915_gem_open i915_gem_init i915_gem_object_bind_to_vm i915_gem_object_set_cache_level i915_context_is_banned i915_gem_object_get_pages i915_gem_mmap_gtt i915_gem_object_create_stolen_for_preallocated i915_pages_create_for_stolen i915_gem_object_create_stolen i915_gem_init_stolen i915_stolen_to_physical gen6_get_stolen_reserved gen7_get_stolen_reserved gen8_get_stolen_reserved i915_capture_error_state A B C "dev=%u, ring=%u, ctx=%p, ctx_vm=%p", REC->dev, REC->ring, REC->to, REC->vm "dev=%u, ctx=%p, ctx_vm=%p", REC->dev, REC->ctx, REC->vm "dev=%u, vm=%p", REC->dev, REC->vm "new_freq=%u", REC->freq "plane=%d, obj=%p", REC->plane, REC->obj "plane=%d, obj=%p", REC->plane, REC->obj "dev=%u, ring=%u, seqno=%u", REC->dev, REC->ring, REC->seqno "dev=%u, ring=%u, seqno=%u, blocking=%s", REC->dev, REC->ring, REC->seqno, REC->blocking ? "yes (NB)" : "no" "dev=%u, ring=%u, seqno=%u", REC->dev, REC->ring, REC->seqno "dev=%u, ring=%x, invalidate=%04x, flush=%04x", REC->dev, REC->ring, REC->invalidate, REC->flush "dev=%u, ring=%u, seqno=%u, flags=%x", REC->dev, REC->ring, REC->seqno, REC->flags "dev=%u, sync-from=%u, sync-to=%u, seqno=%u", REC->dev, REC->sync_from, REC->sync_to, REC->seqno "dev=%d, vm=%p", REC->dev, REC->vm "dev=%d", REC->dev "dev=%d, size=%d, align=%d %s", REC->dev, REC->size, REC->align, REC->flags & (1<<0) ? ", mappable" : "" "obj=%p", REC->obj "obj=%p, %s index=%u %s", REC->obj, REC->gtt ? "GTT" : "CPU", REC->index, REC->write ? ", writable" : "" "obj=%p, offset=%u, len=%u", REC->obj, REC->offset, REC->len "obj=%p, offset=%u, len=%u", REC->obj, REC->offset, REC->len "obj=%p, read=%02x=>%02x, write=%02x=>%02x", REC->obj, REC->read_domains >> 16, REC->read_domains & 0xffff, REC->write_domain >> 16, REC->write_domain & 0xffff "vm=%p, pde=%d, updating %u:%u %s", REC->vm, REC->pde, REC->last, REC->first, __get_str(cur_ptes) "vm=%p, pml4e=%d (0x%llx-0x%llx)", REC->vm, REC->px, REC->start, REC->end "vm=%p, pdpe=%d (0x%llx-0x%llx)", REC->vm, REC->px, REC->start, REC->end "vm=%p, pde=%d (0x%llx-0x%llx)", REC->vm, REC->px, REC->start, REC->end "vm=%p (%s), 0x%llx-0x%llx", REC->vm, __get_str(name), REC->start, REC->end "obj=%p, offset=%016llx size=%x vm=%p", REC->obj, REC->offset, REC->size, REC->vm "obj=%p, offset=%016llx size=%x%s vm=%p", REC->obj, REC->offset, REC->size, REC->flags & (1<<0) ? ", mappable" : "", REC->vm "dev=%d, target=%lu, flags=%x", REC->dev, REC->target, REC->flags "obj=%p, size=%u", REC->obj, REC->size "pipe %c, frame=%u, scanline=%u", ((REC->pipe) + 'A'), REC->frame, REC->scanline "pipe %c, frame=%u, scanline=%u, min=%u, max=%u", ((REC->pipe) + 'A'), REC->frame, REC->scanline, REC->min, REC->max "pipe %c, frame=%u, scanline=%u, min=%u, max=%u", ((REC->pipe) + 'A'), REC->frame, REC->scanline, REC->min, REC->max intel_lr_context_deferred_alloc populate_lr_context intel_init_workaround_bb lrc_setup_wa_ctx_obj gen8_init_common_ring intel_execlists_submission 8 0 ; 0 8 0 ; 0 emit_mocs_control_table emit_mocs_l3cc_table init_status_page init_ring_common intel_ring_workarounds_emit intel_init_pipe_control @ A B C A hsw_unclaimed_reg_detect 0 0 0 0 0 0 0 0 x p intel_guc_ucode_init guc_fw_fetch intel_guc_ucode_load guc_ucode_xfer guc_ucode_xfer_dma guc_client_alloc select_doorbell_cacheline assign_doorbell $ , i
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" C D audio_config_hdmi_pixel_clock ilk_audio_codec_disable ilk_audio_codec_enable g4x_audio_codec_disable g4x_audio_codec_enable intel_audio_codec_enable intel_atomic_setup_scalers intel_plane_atomic_check intel_plane_atomic_set_property intel_plane_atomic_get_property LENOVO 97027RG intel_no_opregion_vbt_callback init_vbt_defaults validate_vbt parse_general_features parse_general_definitions parse_lfp_panel_data parse_lfp_backlight parse_sdvo_panel_data parse_sdvo_device_mapping parse_device_mapping parse_driver_features parse_edp parse_psr parse_mipi parse_ddi_port translate_iboost intel_modeset_setup_hw_state intel_modeset_readout_hw_state intel_sanitize_encoder intel_sanitize_crtc intel_disable_shared_dpll intel_dump_pipe_config intel_dump_crtc_timings i915_redisable_vga_power_on intel_modeset_init intel_atomic_commit intel_connector_check_state check_encoder_state check_crtc_state intel_pipe_config_compare check_shared_dpll_state intel_modeset_pipe_config connected_sink_compute_bpp ironlake_fdi_compute_config ironlake_check_fdi_lanes intel_modeset_checks cherryview_set_cdclk @ ivb_manual_fdi_link_train gen6_fdi_link_train ironlake_fdi_link_train
intel_hpll_vco 0 = UaQ a ( A 0 = UaQ >I 0 = UaQ a 2 Kl6 A 0 = UaQ >I ( 0 = UaQ >I a
i9xx_set_pipeconf intel_enable_pipe intel_disable_pipe i9xx_pfit_disable i9xx_get_refclk >I ;f ? N g5 p N g5 P @
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i9xx_get_initial_plane_config i9xx_crtc_clock_get intel_prepare_shared_dpll cpt_set_fdi_bc_bifurcation intel_enable_shared_dpll ironlake_crtc_compute_clock ironlake_get_refclk ironlake_get_initial_plane_config skylake_pfit_enable lpt_program_iclkip skylake_get_initial_plane_config intel_crtc_init intel_update_pipe_config intel_crtc_atomic_check intel_crtc_page_flip skl_do_mmio_flip C8 RG16XR24XB24AR24AB24XR30XB30YUYVYVYUUYVYVYUYC8 RG16XR24XB24XR30XB30 C8 RG16XR15XR24AR24 i9xx_update_cursor intel_check_cursor_plane intel_update_czclk intel_update_cdclk intel_update_max_cdclk intel_setup_outputs intel_alloc_initial_plane_obj intel_framebuffer_init intel_user_framebuffer_create_handle intel_prepare_plane_fb intel_crtc_restore_mode intel_plane_atomic_calc_changes skl_update_scaler_plane skl_update_scaler intel_release_load_detect_pipe intel_get_load_detect_pipe hsw_disable_pc8 hsw_enable_pc8 ironlake_init_pch_refclk Z ! \& ! `= j ! L
skl_set_cdclk broxton_init_cdclk intel_display_port_aux_power_domain port_to_aux_power_domain port_to_power_domain skl_update_scaler_crtc intel_get_shared_dpll skl_plane_ctl_rotation skl_plane_ctl_tiling skl_plane_ctl_format intel_fb_stride_alignment intel_pin_and_fence_fb_obj intel_tile_height d
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i8xx_fbc_disable i8xx_fbc_enable g4x_fbc_disable g4x_fbc_enable ilk_fbc_enable ilk_fbc_disable gen7_fbc_enable intel_fbc_cancel_work __intel_fbc_update intel_fbc_alloc_cfb set_no_fbc_reason intel_no_fbc_reason_str intel_hpd_irq_storm_reenable_work i915_hotplug_work_func intel_hpd_irq_event intel_hpd_irq_handler intel_hpd_irq_storm_detect 00 0 @ 0@/ 00 . 0, 0` + 0 *` 0ീ ( 0 @? 0x <`@0 : @00 8@0 x 6 0@ 4` 0@ 2@ 0@ `1 0 0 0 `. , h@+@ )`( `>( < 9@ 7 6 4 h `3న @2 @1` 0 0 0 intel_overlay_attrs intel_overlay_put_image intel_overlay_continue intel_psr_enable intel_psr_match_conditions vlv_sideband_rw XB24XR24YUYVYVYUUYVYVYUY XR24YUYVYVYUUYVYVYUY RG16AB24AR24XB24XR24XB30AB30YUYVYVYUUYVYVYUY intel_check_sprite_plane skl_update_plane intel_dsm_detect intel_dsm_pci_probe s~ONT ,intel_dsm intel_dsm_platform_mux_info intel_opregion_setup swsci_setup swsci asle_work asle_set_als_illum asle_set_backlight asle_set_pfit asle_set_pwm_freq asle_set_supported_rotation_angles asle_set_button_array asle_set_convertible asle_set_docking asle_isct_state intel_didl_outputs intel_fbdev_restore_mode intel_fb_initial_config intelfb_create intel_fbdev_init_bios ch7017_dump_regs ch7017_mode_set ch7017_init ch7xxx_dump_regs ch7xxx_readb ch7xxx_writeb ch7xxx_init ivch_dump_regs ivch_read ! " # $ % & ' 1 2 3 4 5 6 7 ivch_reset ivch_write ivch_init ns2501_readb
@ ! " # $ % & ' ~ %(( pO
12 T = $ 1 d s'= # 0 12 F = ns2501_mode_set ns2501_writeb ns2501_mode_valid ns2501_dpms ns2501_init sil164_dump_regs sil164_readb sil164_writeb sil164_init tfp410_dump_regs tfp410_readb tfp410_writeb tfp410_init ACER ZGB Dell Inc. XPS 8700 intel_crt_get_edid intel_crt_detect intel_crt_detect_hotplug intel_ironlake_crt_detect_hotplug valleyview_crt_detect_hotplug intel_crt_detect_ddc intel_crt_load_detect intel_crt_reset intel_ddi_init & p 0 ` 6 E 0 h 6 U + 6 e 0 4 N U h @ + M t U @ f U 4 4 U 4 @ * + M M U M @ f f U bxt_ddi_vswing_sequence intel_ddi_get_config ` @ D @` H L `` P T bxt_ddi_pll_get_hw_state translate_signal_level P p P p P P p P p P P p P p P @ p ` p ` @ p ` p P @ p ` p p P p @ ` 0 0 P p @ ` 0 0 intel_ddi_get_hw_state skl_ddi_pll_select skl_ddi_calculate_wrpll $ x `= K 8 33 bxt_ddi_pll_select hsw_ddi_pll_select hsw_fdi_link_train _
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$ ( * , 0 4 6 8 < @ B D F H L N P T X Z \ ` b # intel_dp_destroy_mst_connector intel_mst_enable_dp intel_mst_pre_enable_dp intel_mst_post_disable_dp intel_mst_disable_dp intel_dp_check_mst_status vlv_initial_power_sequencer_setup intel_dp_init_panel_power_sequencer vlv_power_sequencer_pipe vlv_steal_power_sequencer vlv_detach_power_sequencer edp_panel_vdd_off_sync x `= x Q vlv_power_sequencer_kick intel_dp_init_panel_power_sequencer_registers intel_edp_panel_vdd_sanitize intel_dp_link_down intel_enable_dp vlv_init_panel_power_sequencer edp_panel_vdd_on wait_panel_power_cycle wait_panel_status edp_panel_on wait_panel_on ironlake_set_pll_cpu_edp ironlake_edp_pll_on intel_dp_get_config intel_dp_get_hw_state intel_dp_init_connector intel_dp_force intel_dp_set_property intel_dp_detect intel_dp_detect_dpcd intel_dp_get_dpcd intel_dp_print_rates x K 8 `= x K `= x `= intel_dp_probe_oui intel_dp_probe_mst intel_dp_handle_test_request intel_dp_autotest_edid intel_dp_aux_init intel_dp_aux_ch intel_dp_check_edp intel_edp_init_connector intel_dp_drrs_init intel_dp_set_drrs_state intel_edp_backlight_power intel_edp_drrs_enable intel_dp_hpd_pulse intel_dp_check_link_status ibx_digital_port_connected cpt_digital_port_connected bxt_digital_port_connected vlv_digital_port_connected g4x_digital_port_connected intel_dp_sink_crc intel_dp_sink_crc_stop intel_dp_link_training_clock_recovery intel_dp_set_signal_levels gen7_edp_signal_levels gen6_edp_signal_levels intel_dp_link_training_channel_equalization intel_dp_sink_dpms intel_edp_backlight_off intel_edp_backlight_on edp_panel_off wait_panel_off intel_dp_compute_config x
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? H A @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ B @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ C intel_dsi_init intel_dsi_mode_valid intel_dsi_get_modes intel_dsi_connector_destroy intel_dsi_get_config intel_dsi_get_hw_state intel_dsi_post_disable intel_dsi_disable intel_dsi_clear_device_ready intel_dsi_pre_disable intel_dsi_enable_nop intel_dsi_pre_enable vlv_dsi_device_ready bxt_dsi_device_ready intel_dsi_enable intel_dsi_pre_pll_enable intel_dsi_prepare intel_dsi_compute_config vbt_panel_init generic_exec_sequence mipi_exec_send_packet 2 d vlv_disable_dsi_pll bxt_disable_dsi_pll vlv_enable_dsi_pll vlv_configure_dsi_pll u n 7 y ^ W j 5 q 8 G # D bxt_enable_dsi_pll bxt_get_dsi_pclk vlv_get_dsi_pclk ` 8 ` v ` u ` 8 ` u @ 8 intel_dvo_detect intel_enable_hdmi_audio intel_hdmi_init_connector intel_hdmi_force intel_hdmi_detect g4x_infoframe_index g4x_infoframe_enable hsw_dip_data_reg hsw_infoframe_enable g4x_set_infoframes intel_hdmi_compute_config intel_gmbus_force_bit gmbus_xfer P P P P P $P P P P $P P P P P P $P Apple Macmini1,1 Apple Macmini2,1 MSI A9830IMS Dell Inc. Studio Hybrid 140g Dell Inc. OptiPlex FX170 AOpen i965GMx-IF AOpen
i915GMx-F AOpen
i915GMm-HFS AOpen
i45GMx-I AO00001JW Clientron U800 Clientron E830 ASUSTeK Computer INC. EB1007 ASUSTeK Computer INC.
AT5NM10T-I Hewlett-Packard t5740 Hewlett-Packard hp t5745 Hewlett-Packard hp st5747 MICRO-STAR INTERNATIONAL CO., LTD
MS-7469 Gigabyte Technology Co., Ltd.
D525TUD Supermicro X7SPA-H FUJITSU ESPRIMO Q900 Intel
D410PT Intel D425KT Intel D510MO Intel D525MW intel_lvds_init intel_lvds_set_property intel_lvds_detect Apple Inc. MacBookPro6,2 Apple Inc. MacBookPro8,2 Apple Inc. MacBookPro9,1 TOSHIBA TECRA A11 intel_lvds_compute_config intel_backlight_device_register intel_backlight_device_update_status intel_panel_actually_set_backlight intel_panel_get_backlight i9xx_enable_backlight get_backlight_max_vbt get_backlight_min_vbt i965_enable_backlight vlv_enable_backlight pch_enable_backlight lpt_disable_backlight lpt_enable_backlight bxt_enable_backlight intel_panel_setup_backlight intel_panel_enable_backlight intel_panel_disable_backlight intel_sdvo_init intel_sdvo_write_cmd
! ' ( ) * + , } z g h i j k l U V W X Y Z ^ _ ` [ \ ] a b c d e f M N O { P Q R S T m n o p q t u v w x y intel_sdvo_debug_write intel_sdvo_read_byte intel_sdvo_get_capabilities intel_sdvo_read_response intel_sdvo_output_setup intel_sdvo_dvi_init 320x200 @ @ A 320x240 @ @ A 400x300 @ & , - L M 640x350 @ B ^ _ ~ 640x400 @ J 640x480 @ ~X 704x480 @ 0` 704x576 @ 0r @ A ` a 720x350 @ ?I 0 ^ _ ~ 720x400 @ R 0 720x480 @ b 0 720x540 @ m 0 < = 720x576 @ xt 0 @ A ` a 768x576 @ R{ @ ` @ A ` a 800x600 @ ! ` X Y x y 832x624 @ @ A p q 920x766 @ C 1024x768 @ C @ ` ! 1280x1024 @ T @ ` ! intel_sdvo_get_tv_modes intel_sdvo_get_lvds_modes intel_sdvo_get_ddc_modes intel_sdvo_connector_matches_edid intel_sdvo_detect intel_sdvo_tv_init intel_sdvo_create_enhance_property intel_sdvo_create_enhance_property_tv intel_sdvo_create_enhance_property_lvds intel_sdvo_analog_init intel_sdvo_lvds_init intel_sdvo_get_config intel_enable_sdvo intel_sdvo_write_infoframe intel_sdvo_compute_config $ @ D | Y H "
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failed to load firmware %s (%d)
timeout waiting for GFX clock force-on (%08x)
drivers/gpu/drm/i915/i915_drv.c Runtime resume failed, disabling it (%d)
GEM idle failed, resume might fail
Resume prepare failed: %d, continuing anyway
failed to re-initialize GPU, declaring wedged!
<6>[drm] This hardware requires preliminary hardware support.
See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support
<6>[drm] Simulated gpu hang, resetting stop_rings
<6>[drm] Reset not implemented, but ignoring error for simulated gpu hangs
<5>drm/i915: Resetting chip after gpu hang
!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)) !IS_HASWELL(dev) && !IS_BROADWELL(dev) IS_HSW_ULT(dev) || IS_BDW_ULT(dev) !IS_HSW_ULT(dev) && !IS_BDW_ULT(dev) waiting for GT wells to go %s (%08x)
(I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask timeout waiting for GT wells to go %s
!(dev_priv->rps.enabled && intel_enable_rc6(dev)) device lock contention, deffering suspend
Runtime suspend failed, disabling it (%d)
DRM not initialized, aborting suspend.
state.event != PM_EVENT_SUSPEND && state.event != PM_EVENT_FREEZE hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x
Command parser error, iir 0x%08x
drivers/gpu/drm/i915/i915_irq.c Interrupt register 0x%x is not zero: 0x%08x
enabled_irq_mask & ~interrupt_mask status_mask & PIPE_A_PSR_STATUS_VLV status_mask & PIPE_B_PSR_STATUS_VLV pipe %c: enable_mask=0x%x, status_mask=0x%x
I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events Command parser error, gt_iir 0x%08x
Command parser error, pm_iir 0x%08x
PCH audio power change on port %c
PCH audio power change on port %d
PCH transcoder audio interrupt
PCH transcoder CRC done interrupt
PCH transcoder CRC error interrupt
The master control interrupt lied (GT0)!
The master control interrupt lied (GT1)!
The master control interrupt lied (GT3)!
The master control interrupt lied (PM)!
The master control interrupt lied (DE MISC)!
The master control interrupt lied (DE PORT)!
Fault errors on pipe %c
: 0x%08x The master control interrupt lied (DE PIPE)!
The master control interrupt lied (SDE)!
trying to get scanoutpos for disabled pipe %c
No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx
!dev_priv->l3_parity.which_slice slice >= NUM_L3_SLICES(dev_priv->dev) Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.
dev_priv->l3_parity.which_slice pm_iir & ~dev_priv->pm_rps_events <3>i915: render error detected, EIR: 0x%08x
<3>i915: INSTDONE_%d: 0x%08x
<3>i915: memory refresh error:
<3>i915: pipe %c stat: 0x%08x
Hangcheck timer elapsed... %s idle
<6>[drm] Fake missed irq on %s
drivers/gpu/drm/i915/i915_sysfs.c User requested overclocking to %d
RC6 residency sysfs setup failed
RC6p residency sysfs setup failed
Media RC6 residency sysfs setup failed
l3 parity slice 1 setup failed
error_state sysfs setup failed
No CSR support available for this platform
Unknown stepping info, firmware loading failed
Firmware has wrong CSS header length %u bytes
Firmware has wrong package header length %u bytes
Firmware not supported for %c stepping
Firmware has wrong dmc header length %u bytes
Firmware has wrong mmio count %u
Firmware has wrong mmio address 0x%x
CSR firmware too big (%u) bytes
Memory allocation failed for dmc payload
drivers/gpu/drm/i915/intel_csr.c CSR program storage start is NULL
drivers/gpu/drm/i915/intel_pm.c Unsupported pixel depth for rotation Enabling RC6 states: RC6 %s RC6p %s RC6pp %s
Unknown FSB/MEM found, disable CxSR
FIFO entries required for mode: %ld
Pipe %c FIFO split %d / %d / %d
Wrong MCH_SSKPD value: 0x%08x This can cause underruns.
Primary WM%d too large %u (max %u)
Sprite WM%d too large %u (max %u)
Cursor WM%d too large %u (max %u)
gpu busy, RCS change rejected
!mutex_is_locked(&dev_priv->rps.hw_lock) %s WM%d latency %u (%u.%u usec)
warning: pcode (write) mailbox access failed
timeout waiting for pcode write (%d) to finish
warning: pcode (read) mailbox access failed
timeout waiting for pcode read (%d) to finish
GT fifo had a previous error %x
Failed to set the min frequency
Overclocking supported. Max: %dMHz, Overclock max: %dMHz
Couldn't check for BIOS workaround
You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)
Couldn't fix incorrect rc6 voltage
(pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0 current GPU freq: %d MHz (%u)
setting GPU freq to %d MHz (%u)
pctx_addr != dev_priv->mm.stolen_base + dev_priv->vlv_pctx->stolen->start dev_priv->rps.max_freq < dev_priv->rps.min_freq dev_priv->rps.idle_freq > dev_priv->rps.max_freq dev_priv->rps.efficient_freq < dev_priv->rps.min_freq dev_priv->rps.efficient_freq > dev_priv->rps.max_freq timed out waiting for Punit DDR DVFS request
Punit not acking DDR DVFS request, assuming DDR DVFS is disabled
Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d
Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d
Setting FIFO watermarks - A: %d
self-refresh entries: %d, wm: %d
self-refresh watermark: display plane %d cursor %d
Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d
FIFO watermarks - A: %d, B: %d
Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d
Setting FIFO watermarks - %c: plane=%d, cursor=%d, sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d
<6>[drm] WARN_ON(!wm_changed)
cstate->base.active != intel_crtc->active fmax: %d, fmin: %d, fstart: %d
stuck trying to change perf mode
Adjusting RC6 mask to %d (requested %d, valid %d)
!mutex_is_locked(&dev->struct_mutex) BIOS didn't set up PCBR, fixing up
RP1(Guar) GPU freq: %d MHz (%u)
not enough stolen space for PCTX, disabling
RP1(Guar Freq) GPU freq: %d MHz (%u)
unknown memory frequency 0x%02x
WM latency values increased to avoid potential underruns
Failed to read display plane latency. Disable CxSR
<6>[drm] failed to find known CxSR latency (found ddr%s fsb freq %d, mem freq %d), disabling CxSR
unexpected fall-through in intel_init_pm
SR watermark: display plane %d, cursor %d
display watermark is too large(%d/%ld), disabling
cursor watermark is too large(%d/%ld), disabling
Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d
<6>[drm] RC6 disabled, disabling runtime PM support
Getting nosync-ref while suspended.
drivers/gpu/drm/i915/intel_runtime_pm.c !power_domains->domain_use_count[domain] toggling display PHY side reset
DC9 already programmed to be disabled.
Platform doesn't support DC9.
DC9 already programmed to be enabled.
DC5 still not disabled to enable DC9.
Disabling display power well support
state != PUNIT_PWRGT_PWR_ON(power_well_id) && state != PUNIT_PWRGT_PWR_GATE(power_well_id) state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe) Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)
Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)
timeout setting power well state %08x (%08x)
power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)
power_well->data != PUNIT_POWER_WELL_DISP2D drivers/gpu/drm/i915/intel_drv.h Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)
Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)
Display PHY %d is not power up
Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)
Invalid for power well status to be enabled, unless done by the BIOS, when request is to disable!
DC6 already programmed to be disabled.
Not Disabling PW1, dmc will handle
Platform doesn't support DC6.
DC6 already programmed to be enabled.
Platform doesn't support DC5.
PG2 not disabled to enable DC5.
DC5 already programmed to be enabled.
DC5 cannot be enabled, if platform is runtime-suspended.
PG1 distributing status timeout
PG2 distributing status timeout
Requesting to disable the power well
drivers/gpu/drm/i915/i915_debugfs.c dpcd read (%zu bytes at %u) failed (%zd)
FB tracking busy bits: 0x%08x
FB tracking flip bits: 0x%08x
0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x
crtc_mask: 0x%08x, active: %d, on: %s
%hu %hu %hu %hu %hu %hu %hu %hu VBT: DRRS_type: FIXME: Unrecognized Value Toggling workaround to %i returns %i
expected <%lu bytes into pipe crc control
too many words, allowed <= %d
tokenize failed, a command is %d words
Trying to capture CRC while pipe is off
collecting CRCs for pipe %c, %s
Masking interrupts on rings 0x%08llx
Manually setting uncore sharing to %llu
0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s
bit6 swizzle for X-tiling = %s
bit6 swizzle for Y-tiling = %s
Enabled by kernel parameter: %s
Manually setting min freq to %llu
Manually setting max freq to %llu
Manually setting wedged to %llu Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d
GuC last action command: 0x%x
GuC last action error code: %d
%-24s: %10llu, last seqno 0x%08x %9d
Priority %d, GuC ctx index: %u, PD offset 0x%x
Doorbell id %d, offset: 0x%x, cookie 0x%x
WQ size %d, offset: 0x%x, tail %d
Master Interrupt Control: %08x
Display Engine port interrupt mask: %08x
Display Engine port interrupt identity: %08x
Display Engine port interrupt enable: %08x
Display Engine misc interrupt mask: %08x
Display Engine misc interrupt identity: %08x
Display Engine misc interrupt enable: %08x
North Display Interrupt enable: %08x
North Display Interrupt identity: %08x
North Display Interrupt mask: %08x
South Display Interrupt enable: %08x
South Display Interrupt identity: %08x
South Display Interrupt mask: %08x
Graphics Interrupt enable: %08x
Graphics Interrupt identity: %08x
Graphics Interrupt mask: %08x
Graphics Interrupt mask (%s): %08x
Available Subslice Total: %u
Available Subslice Per Slice: %u
Available EU Per Subslice: %u
Has Subslice Power Gating: %s
Enabled Subslice Per Slice: %u
Enabled EU Per Subslice: %u
n >= obj->base.size >> PAGE_SHIFT drivers/gpu/drm/i915/i915_drv.h Busy frontbuffer bits: 0x%03x
Logical Ring Contexts are disabled
Execlist status: 0x%08X, context: %u
Read pointer: 0x%08X, write pointer 0x%08X
Status buffer %d: 0x%08X, context: %u
%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)
%pK: %s%s%s%s %8zdKiB %02x %02x [ (%sgtt offset: %08llx, size: %08llx (ringbuffer, space: %d, head: %u, tail: %u, last head: %d) fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj !mutex_is_locked(&(dev)->mode_config.fb_lock) user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj Fence %d, pin count = %d, object = Total %d objects, %llu bytes, %llu GTT size
FBC unsupported on this chipset
GPU freq (MHz) Effective CPU freq (MHz) Effective Ring freq (MHz)
Render RC6 residency since boot: %u
Media RC6 residency since boot: %u
RC information inaccurate because somebody holds a forcewake reference
RC6 "Locked to RPn" residency since boot: %u
RC6+ residency since boot: %u
RC6++ residency since boot: %u
Hangcheck active, fires in %dms
ACTHD = 0x%08llx [current 0x%08llx]
PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x
Lowest (RPN) frequency: %dMHz
Nominal (RP1) frequency: %dMHz
Max non-overclocked (RP0) frequency: %dMHz
Max overclocked frequency: %dMHz
efficient (RPe) frequency: %d MHz
PUNIT_REG_GPU_FREQ_STS: 0x%08x
Current CD clock frequency: %d kHz
Max CD clock frequency: %d kHz
Max pixel clock frequency: %d kHz
No flip due on pipe %c (plane %c)
Flip queued on pipe %c (plane %c)
Flip pending (waiting for vsync) on pipe %c (plane %c)
Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d
Flip not associated with any ring
Flip queued on frame %d, (was ready on frame %d), now %d
Stall check waiting for page flip ioctl, Current scanout address 0x%08x
New framebuffer address 0x%08lx
%u [%u] objects, %llu [%llu] bytes in gtt
%u [%u] active objects, %llu [%llu] bytes
%u [%u] inactive objects, %llu [%llu] bytes
%u unbound objects, %llu bytes
%u purgeable objects, %llu bytes
%u pinned mappable objects, %llu bytes
%u fault mappable objects, %llu bytes
id %d:"%s" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x
CRTC %d: pipe: %c, active=%s (size=%dx%d)
fb: %d, pos: %dx%d, size: %dx%d
encoder %d: type: %s, connectors:
connector %d: type: %s, status: %s cursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s
underrun reporting: cpu=%s pch=%s
connector %d: type %s, status: %s
physical dimensions: %dx%dmm
Context on %s with no gem object
Failed to get pages for context object
[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x
CMD: Abnormal blt cmd length! 0x%08X
CMD: Abnormal bsd cmd length! 0x%08X
CMD: Abnormal rcs cmd length! 0x%08X
Failed to get space for pages
dest_obj->pages_pin_count == 0 drivers/gpu/drm/i915/i915_cmd_parser.c CMD: failed to prepare shadow batch
CMD: Failed to set shadow batch to CPU
CMD: Failed to vmap shadow batch
drivers/gpu/drm/i915/i915_drv.h CMD: Unrecognized command: 0x%08X
CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td
CMD: Rejected command: 0x%08X
CMD: Rejected master-only command: 0x%08X
CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)
CMD: Rejected LRM to OACONTROL
CMD: Rejected LRM to masked register 0x%08X
CMD: Rejected LRI to masked register 0x%08X
CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)
CMD: batch set OACONTROL but did not clear it
CMD: Got to the end of the buffer w/o a BBE cmd!
CMD: cmd_parser_init with unknown ring: %d
CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X
CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X
!mutex_is_locked(&pool->dev->struct_mutex) drivers/gpu/drm/i915/i915_gem_batch_pool.c drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_gem_context.c !mutex_is_locked(&dev_priv->dev->struct_mutex) Failed to change address space on context switch
!dev_priv->ring[RCS].last_context dctx->legacy_hw_ctx.rcs_state->active dev_priv->ring[RCS].default_context <6>[drm] Only EXECLIST mode is supported in vgpu.
Disabling HW Contexts; invalid size %d
Failed to create default global context (error %ld)
%s context support initialized
__i915_vma_unbind_no_wait(vma) drivers/gpu/drm/i915/i915_drv.h include/asm-generic/dma-mapping-common.h !mutex_is_locked(&vm->dev->struct_mutex) drivers/gpu/drm/i915/i915_gem_evict.c n >= obj->base.size >> PAGE_SHIFT drivers/gpu/drm/i915/i915_drv.h entry->flags & __EXEC_OBJECT_NEEDS_MAP && !i915_is_ggtt(vma->vm) drivers/gpu/drm/i915/i915_gem_execbuffer.c Invalid object handle %d at index %d
Object %p [handle %d, index %d] appears more than once in object list
!mutex_is_locked(&req->ring->dev->struct_mutex) non-0 rel constants mode on non-RCS
rel surface constants mode invalid on gen5+
execbuf with unknown constants: %d
Unexpected failure to bind target VMA! reloc with multiple write domains: obj %p target %d offset %d read %08x write %08x reloc with read/write non-GPU domains: obj %p target %d offset %d read %08x write %08x Relocation beyond object bounds: obj %p target %d offset %d size %d.
Relocation not 4-byte aligned: obj %p target %d offset %d.
Impossible case in relocation handling
UXA submitting garbage DR4, fixing up
execbuf with unknown ring: %d
execbuf with non bsd ring but with invalid bsd dispatch flags: %d
execbuf with unknown bsd ring: %d
execbuf with invalid ring: %d
RS is only allowed for Haswell, Gen8 and above
Context %u tried to submit while banned
Attempting to use self-modifying batch buffer
Failed to allocate exec list for %d buffers
copy %d exec entries failed %d
failed to copy %d exec entries back to user
failed to copy %d exec entries back to user (%d)
Couldn't read from MCHBAR. Disabling tiling.
Failed to allocate memory for bit 17 record
dev_priv->fence_regs[obj->fence_reg].pin_count <= 0 drivers/gpu/drm/i915/i915_gem_fence.c bogus fence setup with stride: 0x%x, tiling mode: %i
object 0x%08llx not 512K or pot-size 0x%08x aligned
object 0x%08llx [fenceable? %d] not 1M or pot-size (0x%08x) aligned
!ggtt_vma || dev_priv->fence_regs[obj->fence_reg].pin_count > ggtt_vma->pin_count !mutex_is_locked(&req->ring->dev->struct_mutex) drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_gem_gtt.c GGTT view %u not implemented!
First entry = %d; Num entries = %d (max=%d)
Missing switch case (%lu) in %s
i915_is_ggtt(vm) != !!ggtt_view <6>[drm] Memory usable by graphics device = %lluM
<6>[drm] VT-d active for gfx access
<6>[drm] Disabling PPGTT because VT-d is on
disabling PPGTT on pre-B3 step VLV
Failed to map the gtt page table
readq(>t_entries[i-1]) != gen8_pte_encode(addr, level, true) Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)).
Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0))
Failed to get pages for GGTT view type %u!
Failed to get pages for VMA view type %u (%d)!
gtt != vm->pte_encode(addr, level, true, flags) <6>[drm] applying Ironlake quirks for intel_iommu
!list_empty(&ppgtt->base.active_list) !list_empty(&ppgtt->base.inactive_list) PDE #%d mismatch: Actual PDE: %x Expected PDE: %x
Unexpected fault
Addr: 0x%08lx
Address space: %s
Source ID: %d
Type: %d
i915_vma_bind(vma, obj->cache_level, PIN_UPDATE) Forced to use aperture for PDEs
Allocated pde space (%lldM) at GTT entry: %llx
reserving preallocated space: %llx + %zx
clearing unused GTT space: [%lx, %lx]
dev_priv->gtt.base.bind_vma != ggtt_bind_vma start_in + length_in > ppgtt->base.total bitmap_empty(pt->used_ptes, GEN6_PTES) !bitmap_empty(pt->used_ptes, GEN6_PTES) drivers/gpu/drm/i915/i915_gem_gtt.h !bitmap_empty(new_page_tables, I915_PDES) !gen8_pte_count(pd_start, pd_len) !bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4) The allocation has spanned more than 512GB. It is highly likely this is incorrect. !USES_FULL_48BIT_PPGTT(ppgtt->base.dev) drivers/gpu/drm/i915/i915_gem.c vm == &dev_priv->mm.aliasing_ppgtt->base %s vma for this object not found.
!mutex_is_locked(&old->base.dev->struct_mutex) !(old->frontbuffer_bits & frontbuffer_bits) !mutex_is_locked(&new->base.dev->struct_mutex) new->frontbuffer_bits & frontbuffer_bits drivers/gpu/drm/i915/i915_gem_gtt.h global vma for this object not found. (view=%u)
(gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL) drivers/gpu/drm/i915/i915_drv.h Timed out waiting for the gpu reset to complete
Attempting to obtain a purgeable object
!req || !file || req->file_priv context hanging too fast, banning!
gpu hanging too fast, banning!
*_ring_flush_all_caches failed: %d!
i915_gem_object_needs_bit17_swizzle(obj) !mutex_is_locked(&req->ring->dev->struct_mutex) !i915_gem_obj_ggtt_bound_view(obj, view) Attempting to mmap a purgeable buffer
Incomplete copy, wrote %zu of %zu Failed to initialize GuC, error %d%s
PPGTT enable ring #%d failed %d
Context enable ring #%d failed %d
Failed to initialize GPU, declaring it wedged
flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm) (flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE i915_is_ggtt(vm) != !!ggtt_view vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT bo is already pinned in %s with incorrect alignment: offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d, obj->map_and_fenceable=%d
Invalid object (view type=%u) alignment requested %u
Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu
flags & PIN_MAPPABLE && !obj->map_and_fenceable !i915_gem_valid_gtt_space(vma, obj->cache_level) unhandled error in i915_gem_fault: %i
can not change the cache level of pinned objects
drivers/gpu/drm/i915/i915_gem_render_state.c (i) >= PAGE_SIZE / sizeof(u32) <3>Unable to purge GPU memory due lock contention.
<6>Purging GPU memory, %lu bytes freed, %lu bytes still pinned.
<3>%lu and %lu bytes still available in the bound and unbound GPU page lists.
drivers/gpu/drm/i915/i915_gem_stolen.c <6>[drm] DMAR active, disabling use of stolen memory
GTT within stolen memory at 0x%llx-0x%llx
Stolen memory adjusted to 0x%x-0x%x
conflict detected with stolen region: [0x%08x - 0x%08x]
(reg_val & G4X_STOLEN_RESERVED_ADDR1_MASK) < *base Missing switch case (%lu) in %s
Stolen reserved area [0x%08lx - 0x%08lx] outside stolen memory [0x%08lx - 0x%08lx]
Memory reserved for graphics device: %zuK, usable: %luK
creating preallocated stolen object: stolen_offset=%x, gtt_offset=%x, size=%x
failed to allocate stolen space
failed to allocate stolen object
failed to allocate stolen GTT space
drivers/gpu/drm/i915/i915_drv.h creating stolen object: size=%x
drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_gem_userptr.c i915_gem_object_put_pages(obj) n >= obj->base.size >> PAGE_SHIFT drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_gpu_error.c %08x_%08x %8u %02x %02x [ Kernel: 2.6.32-696.20.1.el6.x86_64
Active process (on ring %s): %s [%d]
FAULT_TLB_DATA: 0x%08x 0x%08x
SYNC_0: 0x%08x [last synced 0x%08x]
SYNC_1: 0x%08x [last synced 0x%08x]
SYNC_2: 0x%08x [last synced 0x%08x]
--- gtt_offset = 0x%08x %08x
%s (w/a) --- gtt_offset = 0x%08x
seqno 0x%08x, emitted %ld, tail 0x%08x
out of memory, not capturing error state
<6>[drm] GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.
<6>[drm] Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel
<6>[drm] drm/i915 developers can then reassign to the right component if it's not a kernel issue.
<6>[drm] The gpu crash dump is required to analyze gpu hangs, so please always attach it.
<6>[drm] GPU crash dump saved to /sys/class/drm/card%d/error
drivers/gpu/drm/i915/./i915_trace.h pipe %c, frame=%u, scanline=%u, min=%u, max=%u
i915_pipe_update_vblank_evaded pipe %c, frame=%u, scanline=%u
obj=%p, offset=%016llx size=%x%s vm=%p
obj=%p, offset=%016llx size=%x vm=%p
vm=%p, pde=%d (0x%llx-0x%llx)
i915_page_directory_entry_alloc vm=%p, pdpe=%d (0x%llx-0x%llx)
i915_page_directory_pointer_entry_alloc vm=%p, pml4e=%d (0x%llx-0x%llx)
vm=%p, pde=%d, updating %u:%u %s
obj=%p, read=%02x=>%02x, write=%02x=>%02x
dev=%u, sync-from=%u, sync-to=%u, seqno=%u
dev=%u, ring=%u, seqno=%u, flags=%x
dev=%u, ring=%x, invalidate=%04x, flush=%04x
dev=%u, ring=%u, seqno=%u, blocking=%s
dev=%u, ring=%u, ctx=%p, ctx_vm=%p
!mutex_is_locked(&req->ring->dev->struct_mutex) drivers/gpu/drm/i915/i915_drv.h profile buffer not large enough __index >= (PAGE_SIZE / sizeof(uint32_t)) drivers/gpu/drm/i915/intel_lrc.c !mutex_is_locked(&ring->dev->struct_mutex) !mutex_is_locked(&req->ring->dev->struct_mutex) drivers/gpu/drm/i915/i915_drv.h failed to quiesce %s whilst cleaning up: %d
%s :timed out trying to stop ring
&target->list == &ring->request_list ctx->engine[ring->id].pin_count (I915_READ_MODE(ring) & MODE_IDLE) == 0 ctx->legacy_hw_ctx.rcs_state != NULL INTEL_INFO(ring->dev)->gen < 8 Alloc LRC backing obj failed.
n >= obj->base.size >> PAGE_SHIFT Failed to pin and map ringbuffer %s: %d
MOCS failed to program: expect performance issues.
!i915_gem_obj_is_pinned(ctx_obj) !i915_gem_obj_is_pinned(rb_obj) !intel_irqs_enabled(ring->dev->dev_private) More than 2 already-submitted reqs queued
Lite Restored request removed from queue
Preemption without Lite Restore
More than two context complete events?
Failed get_pages for context obj
non-0 rel constants mode on non-RCS
rel surface constants mode invalid on gen5+
execbuf with unknown constants: %d
WA batch buffer is not initialized for Gen%d
scratch page not allocated for %s
alloc LRC WA ctx backing obj failed.
pin LRC WA ctx backing obj failed: %d
Failed to setup context WA page: %d
wa_ctx_bb failed sanity checks: size %d is not aligned to %d
WA batch buffer initialization failed: %d
table->size > GEN9_NUM_MOCS_ENTRIES drivers/gpu/drm/i915/intel_mocs.c intel_logical_ring_begin failed %d
Platform that should have a MOCS table does not.
%s : timed out trying to stop ring
timed out waiting for the BSD ring to wake up
drivers/gpu/drm/i915/intel_ringbuffer.c request reserved size too small: %d vs %d!
&request->list == &ring->request_list failed to quiesce %s whilst cleaning up: %d
Failed to allocate ringbuffer %s: %d
%s head not reset to zero ctl %08x head %08x tail %08x start %08x
failed to set %s head to zero ctl %08x head %08x tail %08x start %08x
(I915_READ_MODE(ring) & MODE_IDLE) == 0 %s initialization failed [head=%08x], fudging
%s initialization failed ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]
%s: wait for SyncFlush to complete for TLB invalidation timed out
Failed to allocate seqno page
%s pipe control offset: 0x%08x
!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0 Failed to allocate status page
Failed to pin and map ringbuffer %s: %d
Number of Workarounds emitted: %d
wait_mbox == MI_SEMAPHORE_SYNC_INVALID Failed to allocate semaphore bo. Disabling semaphores
Failed to pin semaphore bo. Disabling semaphores
Unclaimed register before interrupt
drivers/gpu/drm/i915/intel_uncore.c loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES Unclaimed register detected %s %s register 0x%x
%s: timed out waiting for forcewake ack to clear.
%s: timed out waiting for forcewake ack request.
GT thread status wait timed out
domain_id >= FW_DOMAIN_ID_COUNT Unclaimed register detected, enabling oneshot unclaimed register reporting. Please use i915.mmio_debug=N for more information.
Timed out waiting for forcewake timers to finish
<6>[drm] No MT forcewake available on Ivybridge, this can result in issues
<6>[drm] when using vblank-synced partial screen updates.
dev_priv->uncore.fw_domains == 0 No GuC firmware known for this platform
GuC firmware pending, path %s
before requesting firmware: GuC fw fetch status %s
fetch GuC fw from %s succeeded, fw %p
firmware file size %zu (minimum %zu, maximum %zu)
GuC firmware version %d.%d, required %d.%d
firmware version %d.%d OK (minimum %d.%d)
GuC fw fetch status SUCCESS, obj %p
GuC fw fetch status FAIL; err %d, fw %p, obj %p
Failed to fetch GuC firmware from %s (error %d)
DMA status 0x%x, GuC status 0x%x
GuC firmware signature verification failed
GuC fw status: fetch %s, load %s
GuC fw %s invalid guc_fw_fetch_status %s [%d]
drivers/gpu/drm/i915/intel_guc_loader.c drivers/gpu/drm/i915/i915_guc_submission.c GUC: host2guc action 0x%X failed. ret=%d status=0x%08X response=0x%08X
n >= obj->base.size >> PAGE_SHIFT drivers/gpu/drm/i915/i915_drv.h !i915_gem_obj_is_pinned(ctx_obj) !i915_gem_obj_is_pinned(rb_obj) Cookie mismatch. Expected %d, returned %d
selected doorbell cacheline 0x%x, next 0x%x, linesize %u
assigned %s priority doorbell id 0x%x
new priority %u client %p: ctx_index %u db_id %u
FAILED to create priority %u GuC client!
Failed to create execbuf guc_client
drivers/gpu/drm/i915/intel_audio.c HDMI audio pixel clock setting for %d not found, falling back to defaults
Configuring HDMI audio for pixel clock %d (0x%08x)
Enable audio codec, %u bytes ELD
Using automatic mode for N value on port %c
Disable audio codec on pipe %c
Disable audio codec on port %c, pipe %c
Enable audio codec on port %c, pipe %c, %u bytes ELD
failed to add audio component (%d)
Enable audio codec on pipe %c, %u bytes ELD
ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]
!drm_modeset_is_locked(&s->dev->mode_config.connection_mutex) drivers/gpu/drm/i915/intel_atomic.c Too many scaling requests %d > %d
Failed to add [PLANE:%d] to drm_state
intel_plane->pipe != intel_crtc->pipe Attached scaler id %u.%u to %s:%d
drivers/gpu/drm/i915/intel_atomic_plane.c Y/Yf tiling required for 90/270!
Unsupported pixel format %s for 90/270!
Falling back to manually reading VBT from VBIOS ROM for %s
BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d
BDB_GD too small (%d). Invalid.
DRRS supported mode is static
DRRS supported mode is seamless
DRRS not supported (VBT input)
Found panel mode in BIOS VBT tables:
Unsupported backlight data entry size %u
PWM backlight not present in VBT (type %u)
VBT backlight PWM modulation frequency %u Hz, active %s, min brightness %u, level %u
Ignore SDVO panel mode from BIOS VBT tables.
Found SDVO panel mode in BIOS VBT tables:
No general definition block is found, unable to construct sdvo mapping.
Unsupported child device size for SDVO mapping.
the SDVO device with slave addr %2x is found on %s port
SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d
Maybe one SDVO port is shared by two SDVO device.
there exists the slave2_addr. Maybe this is a SDVO device with multiple inputs.
No SDVO device info is found in VBT
No general definition block is found, no devices defined.
Expected child device config size for VBT version %u not known; assuming %u
Child device config size %u is too small.
Unexpected child device config size %u (expected %u for VBT version %u)
no child dev is parsed from VBT
No memory space for child device
No eDP BDB found but eDP panel supported.
VBT has unknown eDP link rate value %u
VBT has unknown eDP lane count value %u
VBT has unknown eDP pre-emphasis value %u
VBT has unknown eDP voltage swing value %u
VBT has unknown PSR lines to wait %u
Found MIPI Config block, panel index = %d
No MIPI Sequence found, parsing complete
Unable to parse MIPI Sequence Block v3+
Sequence start is beyond sequence block size, corrupted sequence block
Sequence block detected but no valid configuration
Corrupted sequence/size, bailing out
Sequence elements going beyond block itself. Sequence block parsing failed
MIPI related vbt parsing complete
More than one child device for port %c in VBT.
Port %c VBT info: DP:%d HDMI:%d DVI:%d EDP:%d CRT:%d
Internal DP port %c is TMDS compatible
Analog port %c is also DP or TMDS compatible
Port %c is not DP/TMDS/CRT compatible
Unexpected DDC pin for port B
Unexpected DDC pin for port C
Unexpected DDC pin for port D
Unexpected AUX channel for port A
Unexpected AUX channel for port B
Unexpected AUX channel for port C
Unexpected AUX channel for port D
VBT HDMI level shift for port %c: %d
Unsupported I_boost value found in VBT (%d), display may not work properly
VBT (e)DP boost level for port %c: %d
VBT HDMI boost level for port %c: %d
Unknown pnv display core clock 0x%04x
mismatch in cpu_transcoder (expected %i, found %i)
mismatch in has_pch_encoder (expected %i, found %i)
mismatch in fdi_lanes (expected %i, found %i)
mismatch in fdi_m_n (expected tu %i gmch %i/%i link %i/%i, found tu %i, gmch %i/%i link %i/%i)
mismatch in has_dp_encoder (expected %i, found %i)
mismatch in lane_count (expected %i, found %i)
mismatch in dp_m_n (expected tu %i gmch %i/%i link %i/%i, found tu %i, gmch %i/%i link %i/%i)
mismatch in dp_m2_n2 (expected tu %i gmch %i/%i link %i/%i, found tu %i, gmch %i/%i link %i/%i)
mismatch in dp_m_n (expected tu %i gmch %i/%i link %i/%i, or tu %i gmch %i/%i link %i/%i, found tu %i, gmch %i/%i link %i/%i)
mismatch in base.adjusted_mode.crtc_hdisplay (expected %i, found %i)
mismatch in base.adjusted_mode.crtc_htotal (expected %i, found %i)
mismatch in base.adjusted_mode.crtc_hblank_start (expected %i, found %i)
mismatch in base.adjusted_mode.crtc_hblank_end (expected %i, found %i)
mismatch in base.adjusted_mode.crtc_hsync_start (expected %i, found %i)
mismatch in base.adjusted_mode.crtc_hsync_end (expected %i, found %i)
mismatch in base.adjusted_mode.crtc_vdisplay (expected %i, found %i)
mismatch in base.adjusted_mode.crtc_vtotal (expected %i, found %i)
mismatch in base.adjusted_mode.crtc_vblank_start (expected %i, found %i)
mismatch in base.adjusted_mode.crtc_vblank_end (expected %i, found %i)
mismatch in base.adjusted_mode.crtc_vsync_start (expected %i, found %i)
mismatch in base.adjusted_mode.crtc_vsync_end (expected %i, found %i)
mismatch in pixel_multiplier (expected %i, found %i)
mismatch in has_hdmi_sink (expected %i, found %i)
mismatch in limited_color_range (expected %i, found %i)
mismatch in has_infoframe (expected %i, found %i)
mismatch in has_audio (expected %i, found %i)
mismatch in base.adjusted_mode.flags(DRM_MODE_FLAG_INTERLACE) (expected %i, found %i)
mismatch in base.adjusted_mode.flags(DRM_MODE_FLAG_PHSYNC) (expected %i, found %i)
mismatch in base.adjusted_mode.flags(DRM_MODE_FLAG_NHSYNC) (expected %i, found %i)
mismatch in base.adjusted_mode.flags(DRM_MODE_FLAG_PVSYNC) (expected %i, found %i)
mismatch in base.adjusted_mode.flags(DRM_MODE_FLAG_NVSYNC) (expected %i, found %i)
mismatch in gmch_pfit.control (expected 0x%08x, found 0x%08x)
mismatch in gmch_pfit.pgm_ratios (expected %i, found %i)
mismatch in gmch_pfit.lvds_border_bits (expected 0x%08x, found 0x%08x)
mismatch in pipe_src_w (expected %i, found %i)
mismatch in pipe_src_h (expected %i, found %i)
mismatch in pch_pfit.enabled (expected %i, found %i)
mismatch in pch_pfit.pos (expected 0x%08x, found 0x%08x)
mismatch in pch_pfit.size (expected 0x%08x, found 0x%08x)
mismatch in scaler_state.scaler_id (expected %i, found %i)
mismatch in ips_enabled (expected %i, found %i)
mismatch in double_wide (expected %i, found %i)
mismatch in ddi_pll_sel (expected 0x%08x, found 0x%08x)
mismatch in shared_dpll (expected %i, found %i)
mismatch in dpll_hw_state.dpll (expected 0x%08x, found 0x%08x)
mismatch in dpll_hw_state.dpll_md (expected 0x%08x, found 0x%08x)
mismatch in dpll_hw_state.fp0 (expected 0x%08x, found 0x%08x)
mismatch in dpll_hw_state.fp1 (expected 0x%08x, found 0x%08x)
mismatch in dpll_hw_state.wrpll (expected 0x%08x, found 0x%08x)
mismatch in dpll_hw_state.spll (expected 0x%08x, found 0x%08x)
mismatch in dpll_hw_state.ctrl1 (expected 0x%08x, found 0x%08x)
mismatch in dpll_hw_state.cfgcr1 (expected 0x%08x, found 0x%08x)
mismatch in dpll_hw_state.cfgcr2 (expected 0x%08x, found 0x%08x)
mismatch in pipe_bpp (expected %i, found %i)
mismatch in base.adjusted_mode.crtc_clock (expected %i, found %i)
mismatch in port_clock (expected %i, found %i)
Bad HPLL VCO (HPLLVCO=0x%02x)
Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x
Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x
Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x
drivers/gpu/drm/i915/intel_display.c Current CD clock rate: %d kHz
scaler_user index %u.%u: Staged freeing scaler id %d scaler_users = 0x%x
scaler_user index %u.%u: src %ux%u dst %ux%u size is out of scaler range
scaler_user index %u.%u: staged scaling request for %ux%u->%ux%u scaler_users = 0x%x
Updating scaler for [CRTC:%i] scaler_user index %u.%u
using SSC reference clock of %d kHz
clock->n == 0 || clock->p == 0 clock->n + 2 == 0 || clock->p == 0 Unknown DPLL mode %08x in programmed mode
I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE (tmp & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe) crtc->config->scaler_state.scaler_id < 0 Requesting pfit without getting a scaler first
for crtc_state = %p scaler_id = %d
!drm_modeset_is_locked(&dev->mode_config.connection_mutex) FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i
Updating scaler for [PLANE:%d] scaler_user index %u.%u
[PLANE:%d] scaling with color key not allowed [PLANE:%d] FB:%d unsupported scaling format 0x%x
[CRTC:%i] has [PLANE:%i] with fb %i
[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i
Missing switch case (%lu) in %s
Suspending crtc's failed with %i
[CRTC:%d]%s config %p for pipe %c
fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u
dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u
dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u
crtc timings: %d %d %d %d %d %d %d %d %d, type: 0x%x flags: 0x%x
num_scalers: %d, scaler_users: 0x%x, scaler_id: %d
gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x
pch pfit: pos: 0x%08x, size: 0x%08x, %s
ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x
ddi_pll_sel: %u; dpll_hw_state: ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x
ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x
dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, fp0: 0x%x, fp1: 0x%x
%s PLANE:%d plane: %u.%u idx: %d disabled, scaler_id = %d
%s PLANE:%d plane: %u.%u idx: %d enabled FB:%d, fb = %ux%u format = 0x%x scaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u
!pll->get_hw_state(dev_priv, pll, &pipe_config->dpll_hw_state) unknown pipe linked to edp transcoder
FDI_RX_IIR before link train 0x%x
FDI train 1 fail on vswing %d
FDI train 2 fail on vswing %d
Something enabled VGA plane, disabling it
mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))
mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))
<6>[drm] Backlight polarity reversed on %s
<6>[drm] applying backlight present quirk
<6>[drm] applying inverted panel brightness quirk
<6>[drm] applying lvds SSC disable quirk
<6>[drm] applying pipe b force quirk
<6>[drm] applying pipe a force quirk
plane %c assertion failure, should be disabled but not
<6>[drm] plane %c assertion failure, should be disabled but not
plane %c assertion failure, should be off on pipe %c but is still active
<6>[drm] plane %c assertion failure, should be off on pipe %c but is still active
plane %d assertion failure, should be off on pipe %c but is still active
<6>[drm] plane %d assertion failure, should be off on pipe %c but is still active
sprite %c assertion failure, should be off on pipe %c but is still active
<6>[drm] sprite %c assertion failure, should be off on pipe %c but is still active
FDI TX state assertion failure (expected %s, current %s)
<6>[drm] FDI TX state assertion failure (expected %s, current %s)
FDI RX state assertion failure (expected %s, current %s)
<6>[drm] FDI RX state assertion failure (expected %s, current %s)
PCH DP (0x%08x) enabled on transcoder %c, should be disabled
<6>[drm] PCH DP (0x%08x) enabled on transcoder %c, should be disabled
IBX PCH dp port still using transcoder B
<6>[drm] IBX PCH dp port still using transcoder B
PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled
<6>[drm] PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled
IBX PCH hdmi port still using transcoder B
<6>[drm] IBX PCH hdmi port still using transcoder B
transcoder assertion failed, should be off on pipe %c but is still active
<6>[drm] transcoder assertion failed, should be off on pipe %c but is still active
WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)))
<6>[drm] WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)))
PCH refclk assertion failure, should be active but is disabled
<6>[drm] PCH refclk assertion failure, should be active but is disabled
pipe %c assertion failure (expected %s, current %s)
<6>[drm] pipe %c assertion failure (expected %s, current %s)
I915_READ(PFIT_CONTROL) & PFIT_ENABLE panel assertion failure, pipe %c regs locked
<6>[drm] panel assertion failure, pipe %c regs locked
FDI RX PLL assertion failure (expected %s, current %s)
<6>[drm] FDI RX PLL assertion failure (expected %s, current %s)
asserting DPLL %s with no DPLL
%s assertion failure (expected %s, current %s)
<6>[drm] %s assertion failure (expected %s, current %s)
!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))) disable %s (active %d, on? %d) for crtc %d
enable %s (active %d, on? %d) for crtc %d
PLL state assertion failure (expected %s, current %s)
<6>[drm] PLL state assertion failure (expected %s, current %s)
trying to change cdclk frequency with cdclk not enabled
failed to inform pcode about cdclk change
cdclk requested %d kHz but got %d kHz
Switching back to LCPLL failed
PCode CDCLK freq change notify failed (err %d, freq %d)
timout waiting for DE PLL unlock
timeout waiting for DE PLL lock
PCode CDCLK freq set failed, (err %d, freq %d)
timed out waiting for port %c ready: got 0x%x, expected 0x%x
dev_priv->display.get_display_clock_speed(dev) != dev_priv->cdclk_freq I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND timed out waiting for CDclk change
WARN_ON(drm_crtc_vblank_get(crtc) == 0)
<6>[drm] WARN_ON(drm_crtc_vblank_get(crtc) == 0)
128-bit pixels are not supported for display! pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x
pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x
drivers/gpu/drm/i915/intel_drv.h Updating pipe size %ix%i -> %ix%i
rejecting invalid cloning configuration
pipe_config->shared_dpll != DPLL_ID_PRIVATE [CRTC:%d] crtc restore failed, out of memory !mutex_is_locked(&req->ring->dev->struct_mutex) drivers/gpu/drm/i915/i915_drv.h !mutex_is_locked(&obj->base.dev->struct_mutex) Couldn't get view from plane state! Cursor dimension %dx%d not supported
CHV cursor C not allowed to straddle the left screen edge
!mutex_is_locked(&dev->struct_mutex) tiling_mode doesn't match fb modifier
Unsupported fb modifier 0x%llx!
pitch (%d) must be at least %u byte aligned
%s pitch (%u) must be at less than %d
pitch (%d) must match tiling stride (%d)
attempting to use a userptr for a framebuffer, denied
Kicking stuck page flip: queued at %d, now %d
failed to inform PCU about cdclk change
CRTC:%d using pre-allocated %s
CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)
Couldn't find PLL settings for mode!
failed to find PLL for pipe %c
waitqueue_active(&dev_priv->pending_flip_queue) wait_event_timeout(dev_priv->pending_flip_queue, !intel_crtc_has_pending_flip(crtc), 60*HZ) == 0 ggtt vma for display object not found! (view=%u)
drm_rect_width(&plane_state->src) == 0 Y tiling bo slipped through, driver bug!
failed to pin boot fb on pipe %d
flip queue: previous flip completed, continuing
flip queue: crtc already busy
DSI PLL state assertion failure (expected %s, current %s)
<6>[drm] DSI PLL state assertion failure (expected %s, current %s)
cursor on pipe %c assertion failure (expected %s, current %s)
<6>[drm] cursor on pipe %c assertion failure (expected %s, current %s)
disabling pfit, current: 0x%08x
PCH VGA enabled on transcoder %c, should be disabled
<6>[drm] PCH VGA enabled on transcoder %c, should be disabled
PCH LVDS enabled on transcoder %c, should be disabled
<6>[drm] PCH LVDS enabled on transcoder %c, should be disabled
failed to disable transcoder %c
Failed to disable PCH transcoder
FDI TX PLL assertion failure, should be active but is disabled
<6>[drm] FDI TX PLL assertion failure, should be active but is disabled
!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) plane %c assertion failure (expected %s, current %s)
<6>[drm] plane %c assertion failure (expected %s, current %s)
sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000) Timed out waiting for IPS enable
sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0) Timed out waiting for IPS disable
failed to enable transcoder %c
mode set failed: pipe %c stuck
SBI_SSCDIVINTPHASE_DIVSEL(divsel) & ~SBI_SSCDIVINTPHASE_DIVSEL_MASK iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x
Failed to enable PCH transcoder
i915 does not yet support async commit
connector enabled without attached crtc
<6>[drm] connector enabled without attached crtc
connector is active, but attached crtc isn't
<6>[drm] connector is active, but attached crtc isn't
atomic encoder doesn't match attached encoder
<6>[drm] atomic encoder doesn't match attached encoder
attached encoder crtc differs from connector crtc
<6>[drm] attached encoder crtc differs from connector crtc
attached crtc is active, but connector isn't
<6>[drm] attached crtc is active, but connector isn't
best encoder set without crtc!
<6>[drm] best encoder set without crtc!
connector's atomic encoder doesn't match legacy encoder
<6>[drm] connector's atomic encoder doesn't match legacy encoder
connector's crtc doesn't match encoder crtc
<6>[drm] connector's crtc doesn't match encoder crtc
encoder's enabled state mismatch (expected %i, found %i)
<6>[drm] encoder's enabled state mismatch (expected %i, found %i)
encoder detached but still enabled on pipe %c.
<6>[drm] encoder detached but still enabled on pipe %c.
crtc active state doesn't match with hw state (expected %i, found %i)
<6>[drm] crtc active state doesn't match with hw state (expected %i, found %i)
transitional active state does not match atomic hw state (expected %i, found %i)
<6>[drm] transitional active state does not match atomic hw state (expected %i, found %i)
[ENCODER:%i] active %i with crtc active %i
<6>[drm] [ENCODER:%i] active %i with crtc active %i
Encoder connected to wrong pipe %c
<6>[drm] Encoder connected to wrong pipe %c
<6>[drm] pipe state doesn't match!
more active pll users than references: %i vs %i
<6>[drm] more active pll users than references: %i vs %i
pll in active use but not on in sw tracking
<6>[drm] pll in active use but not on in sw tracking
pll in on but not on in use in sw tracking
<6>[drm] pll in on but not on in use in sw tracking
pll on state mismatch (expected %i, found %i)
<6>[drm] pll on state mismatch (expected %i, found %i)
pll active crtcs mismatch (expected %i, found %i)
<6>[drm] pll active crtcs mismatch (expected %i, found %i)
pll enabled crtcs mismatch (expected %i, found %i)
<6>[drm] pll enabled crtcs mismatch (expected %i, found %i)
<6>[drm] pll hw state mismatch
FDI mPHY reset assert timeout
FDI mPHY reset de-assert timeout
has_panel %d has_lvds %d has_ck505 %d
<6>[drm] CRTC for pipe %c enabled
D_COMP RCOMP still in progress
Invalid cursor width/stride, width=%u, stride=%u
requested cdclk (%d kHz) exceeds max (%d kHz)
[CONNECTOR:%d:%s], [ENCODER:%d:%s]
Couldn't release load detect pipe.
unknown plane in flip command
!intel_fb->obj->framebuffer_references-- [CONNECTOR:%d:%s] checking for sink bpp constrains
clamping display bpp (was %d) to EDID reported max of %d
clamping display bpp (was %d) to default limit of 24
checking fdi config on pipe %c, lanes %i
invalid fdi lane config on pipe %c: %i lanes
only 2 lanes on haswell, required: %i lanes
invalid shared fdi lane config on pipe %c: %i lanes
only 2 lanes on pipe %c: required %i lanes
fdi link B uses too many lanes to enable link C
fdi link bw constraint, reducing pipe bpp to %i
loop in pipe configuration computation
CRTC bw constrained, retrying
hw max bpp: %i, pipe bpp: %i, dithering: %i
rejecting conflicting digital port configuration
no pipe available for load-detect
creating tmp fb for load-detection
reusing fbdev for load-detection framebuffer
failed to allocate framebuffer for load-detection
failed to set mode on load-detect pipe
[CRTC:%d] hw state readout: %s
%s hw state readout: crtc_mask 0x%08x, on %i
[ENCODER:%d:%s] hw state readout: %s, pipe %c
[CONNECTOR:%d:%s] hw state readout: %s
drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode) [ENCODER:%d:%s] has active connectors but no active pipe!
[ENCODER:%d:%s] manually disabled
[CRTC:%d] wrong plane connection detected!
[CRTC:%d] hw state adjusted, was %s, now %s
drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0 %s enabled but not in use, disabling
Restoring old state failed with %i
__i915_wait_request(mmio_flip->req, mmio_flip->crtc->reset_counter, false, NULL, &mmio_flip->i915->rps.mmioflips) SSC %sabled by BIOS, overriding VBT which says %sabled
Unknown platform. Assuming 133 MHz CDCLK
swapping pipes & planes for FBC
drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe pipe %c sprite %c init failed: %d
enabled FBC, pitch %d, yoff %d, plane %c
FBC enabled but currently disabled in hardware mode incompatible with compression mode too large for compression framebuffer not tiled or fenced framebuffer stride not supported Missing switch case (%lu) in %s
drivers/gpu/drm/i915/intel_fbc.c !mutex_is_locked(&dev_priv->fbc.lock) cancelling pending FBC enable
<6>[drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.
reserved %llu bytes of contiguous stolen space for FBC, threshold: %d
<6>drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.
disabling active FBC for update
Failed to allocate FBC work structure
unsupported config, disabling FBC
drivers/gpu/drm/i915/intel_fifo_underrun.c <6>[drm] uncleared pch fifo underrun on pch transcoder %c
<6>[drm] PCH transcoder %c FIFO underrun
<6>[drm] uncleared fifo underrun on pipe %c
<6>[drm] CPU pipe %c FIFO underrun
!mutex_is_locked(&dev->struct_mutex) drivers/gpu/drm/i915/intel_frontbuffer.c Reenabling HPD on connector %s
running encoder hotplug functions
drivers/gpu/drm/i915/intel_hotplug.c <6>[drm] HPD interrupt storm detected on connector %s: switching from hotplug detection to polling
Connector %s (pin %i) received hotplug event.
!mutex_is_locked(&dev->mode_config.mutex) [CONNECTOR:%d:%s] status updated from %s to %s
Received HPD interrupt on pin %d although disabled
Received HPD interrupt on PIN %d - cnt: 0
HPD interrupt storm detected on PIN %d
Received HPD interrupt on PIN %d - cnt: %d
Overlay, status: 0x%08x, interrupt: 0x%08x
drivers/gpu/drm/i915/intel_overlay.c failed to attach phys overlay regs
failed to pin overlay register bo
failed to move overlay register bo into the GTT
<6>[drm] initialized overlay support
!mutex_is_locked(&req->ring->dev->struct_mutex) drivers/gpu/drm/i915/i915_drv.h !mutex_is_locked(&dev->struct_mutex) !drm_modeset_is_locked(&dev->mode_config.connection_mutex) buffer used for overlay image can not be tiled
IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE) I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE drivers/gpu/drm/i915/intel_psr.c Timed out waiting for PSR Idle for re-enable
vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe) Timed out waiting for PSR Idle State
PSR transition took longer than expected
PSR not supported on this platform
PSR not supported by this panel
!drm_modeset_is_locked(&dev->mode_config.connection_mutex) !drm_modeset_is_locked(&crtc->mutex) PSR condition failed: Stereo 3D is Enabled
PSR condition failed: Interlaced is Enabled
PSR condition failed: Link Standby requested/needed but not supported on this platform
!mutex_is_locked(&dev_priv->sb_lock) drivers/gpu/drm/i915/intel_sideband.c timeout waiting for SBI to become ready
timeout waiting for SBI to complete write transaction
timeout waiting for SBI to complete read transaction
IOSF sideband idle wait (%s) timed out
IOSF sideband finish wait (%s) timed out
!mutex_is_locked(&dev_priv->rps.hw_lock) DPIO read pipe %c reg 0x%x == 0x%x
Unsuitable framebuffer for plane
drivers/gpu/drm/i915/intel_sprite.c Horizontal scaling factor out of limits
Vertical scaling factor out of limits
src->x1 < (int) state->base.src_x || src->y1 < (int) state->base.src_y || src->x2 > (int) state->base.src_x + state->base.src_w || src->y2 > (int) state->base.src_y + state->base.src_h Source dimensions exceed hardware limits
plane = %d PS_PLANE_SEL(plane) = 0x%x
Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d
drm_crtc_vblank_get(&crtc->base) Potential atomic update failure on pipe %c
no _DSM method for intel device
failed to get supported _DSM functions
vga_switcheroo: detected DSM switching method %s handle
<6>[drm] ACPI BIOS requests an excessive sleep of %u ms, using %u ms instead
SWSCI request already in progress
graphic opregion physical addr: 0x%x
Public ACPI methods supported
SWSCI BIOS requested (%08x) SBCB callbacks that are not supported (%08x)
SWSCI GBDA callbacks %08x, SBCB callbacks %08x
No request on ASLC interrupt 0x%08x
updating opregion backlight %d/255
Button array event is not supported (nothing)
Button array event is not supported (rotation lock)
Button array event is not supported (volume down)
Button array event is not supported (volume up)
Button array event is not supported (windows)
Button array event is not supported (power)
Convertible is not supported (clamshell)
Convertible is not supported (slate)
Docking is not supported (docked)
Docking is not supported (undocked)
i >= ARRAY_SIZE(opregion->acpi->did2) drivers/gpu/drm/i915/intel_opregion.c More than %u outputs detected via ACPI
More than %u outputs in connector list
unsupported intel_encoder type %d
drivers/gpu/drm/i915/intel_fbdev.c connector %s not enabled, skipping
connector %s is disabled by user, skipping
connector %s has no encoder or crtc, skipping
fallback: cloned configuration
looking for cmdline mode on connector %s
looking for preferred mode on connector %s %d
using first mode listed on connector %s
looking for current mode on connector %s
connector %s on pipe %c [CRTC:%d]: %dx%d%s
fallback: Not all outputs enabled
Not using firmware configuration
INTEL_INFO(dev)->num_pipes == 0 pipe %c not active or no fb, skipping
found possible fb from plane %c
no active fbs found, not using BIOS config
checking plane %c for BIOS fb
fb not wide enough for plane %c (%d vs %d)
pipe %c area: %dx%d, bpp: %d, size: %d
fb not big enough for plane %c (%d vs %d)
fb big enough for plane %c (%d >= %d)
BIOS fb not suitable for all pipes, not using
re-used BIOS config but lost an fb on crtc %d
using BIOS fb for initial console
failed to allocate framebuffer
BIOS fb too small (%dx%d), we require (%dx%d), releasing it
no BIOS fb, allocating a new one
allocated %dx%d fb: 0x%08llx, bo %p
CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT: %02x
CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT: %02x
CH7017_VERTICAL_ACTIVE_LINE_OUTPUT: %02x
CH7017_ACTIVE_INPUT_LINE_OUTPUT: %02x
CH7017_LVDS_PLL_VCO_CONTROL: %02x
CH7017_LVDS_PLL_FEEDBACK_DIV: %02x
Registers before mode setting
ch701x not detected, got %d: from %s slave %d.
Unable to read register 0x%02x from %s:%02x.
Unable to write register 0x%02x to %s:%d.
ch7xxx not detected; got 0x%02x from %s slave %d.
Detected %s chipset, vendor/device ID 0x%02x/0x%02x
Unable to read register 0x%02x from %s:%02x.
Unable to write register 0x%02x to %s:%d.
ivch detect failed due to address mismatch (%d vs %d)
Unable to read register 0x%02x from %s:0x%02x.
Unable to write register 0x%02x to %s:%d
set mode (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d).
Detailed requested mode settings are:
clock : %d kHz
hdisplay : %d
hblank start : %d
hblank end : %d
hsync start : %d
hsync end : %d
htotal : %d
hskew : %d
vdisplay : %d
vblank start : %d
hblank end : %d
vsync start : %d
vsync end : %d
vtotal : %d
is mode valid (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d)
Trying set the dpms of the DVO to %i
ns2501 not detected got %d: from %s Slave %d.
init ns2501 dvo controller successfully!
Unable to read register 0x%02x from %s:%02x.
Unable to write register 0x%02x to %s:%d.
sil164 not detected got %d: from %s Slave %d.
init sil164 dvo controller successfully!
Unable to read register 0x%02x from %s:%02x.
Unable to write register 0x%02x to %s:%d.
tfp410 not detected got VID %X: from %s Slave %d.
tfp410 not detected got DID %X: from %s Slave %d.
CRT GMBUS EDID read failed, retry using GPIO bit-banging
drivers/gpu/drm/i915/intel_crt.c CRT detected via DDC:0x50 [EDID]
CRT not detected via DDC:0x50 [EDID reports a digital panel]
CRT not detected via DDC:0x50 [no valid EDID found]
trigger hotplug detect cycle: adpa=0x%x
timed out waiting for FORCE_TRIGGER ironlake hotplug adpa=0x%x, result %d
valleyview hotplug adpa=0x%x, result %d
timed out waiting for FORCE_DETECT to go off <6>[drm] Skipping CRT initialization for %s
VBT says port %c is not DVI/HDMI/DP compatible, respect it
Timeout waiting for DDI BUF %c idle bit
Vswing programming not done for encoder %d
Disabled scaling while ouniqetrangenmethod was set Unsupported voltage swing/pre-emphasis level: 0x%x
%d encoders on crtc for pipe %c
drivers/gpu/drm/i915/intel_ddi.c intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL FDI link training done on step %d
pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE Invalid encoder type %d for pipe %c
compute_config() on unknown output!
lane stagger config different for lane 01 (%08x) and 23 (%08x)
timeout during PHY%d power on
No pipe for ddi port %c found
No valid divider found for %dHz
failed to find PLL for pipe %c
no PLL dividers found for clock %d pipe %c
spll->hw_state.spll != crtc_state->dpll_hw_state.spll pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp
ddi translation table missing
Disabling mst crtc failed with %i
drivers/gpu/drm/i915/intel_dp_mst.c Timed out waiting for ACT sent
failed to %s sink power state
drivers/gpu/drm/i915/intel_dp.c (I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0 invalid max DP link bw val %x, using 1.62Gbps
panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x
picked pipe %c power sequencer for port %c
drivers/gpu/drm/i915/intel_drv.h skipping pipe %c power seqeuncer kick due to port %c being active
kicking pipe %c power sequencer for port %c
cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d
vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d
panel power up delay %d, power down delay %d, power cycle delay %d
backlight on delay %d, off delay %d
PP_STATUS: 0x%08x PP_CONTROL: 0x%08x
detaching pipe %c power sequencer from port %c
pipe != PIPE_A && pipe != PIPE_B stealing pipe %c power sequencer from port %c
stealing pipe %c power sequencer from active eDP port %c
no initial power sequencer for port %c
initial power sequencer for port %c: pipe %c
VDD left on by BIOS, adjusting state tracking
dp port still on, should be off
160MHz cpu eDP clock, might need ilk devA w/a
DP training pattern 3 not supported
mask %08x value %08x status %08x control %08x
Panel status timeout: status %08x control %08x
Turn eDP port %c panel power off
Need eDP port %c VDD to turn off panel
Wait for panel power off time
<6>[drm] eDP port %c VDD not forced on pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp
No pipe for dp port 0x%x found
Refresh rate should be positive non-zero.
DRRS: intel_crtc not initialized
Only Seamless DRRS supported.
DRRS requested for previously set RR...ignoring
eDP encoder disabled. CRTC not Active
eDP Refresh Rate set to : %dHz
Missing switch case (%lu) in %s
Sink CRC couldn't be stopped properly
Unreliable Sink CRC counter: Current returned CRC is identical to the previous one
Panel is unable to calculate any CRC after 6 vblanks
Unsupported voltage swing/pre-emphasis level:0x%x
DP link computation with max lane count %i max bw %d pixel clock %iKHz
clamping bpp for eDP panel to BIOS-provided %i
DP link bw %02x rate select %02x lane count %d clock %d bpp %d
DP link bw required %i available %i
failed to enable link training
too many full retries, give up
too many voltage retries, give up
failed to update link training
5.4 Gbps link rate without HBR2/TPS3 support
failed to start channel equalization
Channel EQ done. DP Training successful
Timed out waiting for DP idle patterns
channel EQ not ok, retraining
failed to get ESI - device may have failed
Display Port TPS3 support: source %s, sink %s
Broken DP branch device, ignoring
Could not read test request from sink
EDID read had %d NACKs, %d DEFERs
Failed to write EDID checksum
Could not write test response to sink
CP or sink specific irq unhandled
IS_VALLEYVIEW(dev) && is_edp(intel_dp) && port != PORT_B && port != PORT_C Adding %s connector on port %c
drm_dp_aux_register() for %s failed (%d)
sysfs_create_link() for %s failed (%d)
<6>[drm] failed to retrieve link info, disabling eDP
DRRS supported for Gen7 and above
Downclock mode is not found. DRRS not supported
seamless DRRS supported for eDP panel.
using pipe %c for initial backlight setup
!drm_modeset_is_locked(&dev->mode_config.connection_mutex) Test request in short pulse not handled
%s: channel EQ not ok, retraining
ignoring long hpd on eDP port %c
MST device may have disappeared %d vs %d
panel power control backlight %s
eDP port %c panel power wasn't enabled
eDP port %c VDD already requested on
<6>[drm] eDP port %c VDD already requested on
eDP powered off while attempting aux channel communication.
dp_aux_ch not started status 0x%08x
send_bytes > 20 || recv_size > 20 dp aux hw did not signal timeout (has irq: %i)!
dp_aux_ch not done status 0x%08x
dp_aux_ch receive error status 0x%08x
dp_aux_ch timeout status 0x%08x
Turn eDP port %c panel power on
eDP port %c panel power already on
initializing pipe %c power sequencer for port %c
Unsupported Mipi device to reg base Timeout waiting for HS/LP DATA FIFO !full
Timeout waiting for HS/LP CTRL FIFO !full
Timeout waiting for read data.
Same special packet %02x twice in a row.
Video mode command 0x%08x send failed.
Unsupported MIPI element, skipping sequence execution
Burst mode freq is less than computed
Values crossing maximum limits, restricting to max values
Dual link: DSI_DUAL_LINK_FRONT_BACK
Dual link: DSI_DUAL_LINK_PIXEL_ALT
Generic Read not yet implemented or used
DCS Read not yet implemented or used
Timeout waiting for PLL lock deassertion
DSI PLL already enabled. Disabling it.
drivers/gpu/drm/i915/intel_dsi_pll.c Cant get a suitable ratio from DSI PLL ratios
Configure DSI PLL failed, abort PLL enable
Timed out waiting for DSI PLL to lock
Invalid DSI pll ratio(%u) programmed
bpp match assertion failure (expected %d, current %d)
HDMI port enabled, expecting disabled
drivers/gpu/drm/i915/intel_hdmi.c !drm_modeset_is_locked(&dev->mode_config.connection_mutex) Writing DIP with CTL reg disabled
Enabling HDMI audio on pipe %c
drivers/gpu/drm/i915/intel_drv.h Missing switch case (%lu) in %s
DIP already enabled on port %c
video DIP still enabled on port %c
video DIP already enabled on port %c
picking bpc to 12 for HDMI output
picking bpc to 8 for HDMI output
forcing pipe bpc to %i for HDMI
unsupported HDMI clock, rejecting mode
%sabling bit-banging on %s. force bit now %d
!intel_gmbus_is_valid_pin(dev_priv, pin) drivers/gpu/drm/i915/intel_i2c.c GMBUS [%s] timed out waiting for idle
GMBUS [%s] timed out after NAK
GMBUS [%s] NAK for addr: %04x %c(%d)
GMBUS [%s] NAK on first message, retry
<6>[drm] GMBUS [%s] timed out, falling back to bit banging on pin %d
<6>[drm] Skipping LVDS initialization for %s
<6>[drm] Forcing lvds to dual link mode on %s
<6>[drm] Skipping forced modeset for %s
LVDS is not present in VBT, but enabled anyway
Panel power timings uninitialized, setting defaults
using preferred mode from EDID: detected %s-link lvds configuration
lid notifier registration failed
No LVDS modes found, disabling.
timed out waiting for panel to power off
forcing display bpp (was %d) to LVDS (%d)
timed out waiting for panel to power on
Apple Mac Mini (Core 2 series) drivers/gpu/drm/i915/intel_panel.c pipe != PIPE_A && pipe != PIPE_B backlight frequency not specified in VBT
backlight frequency setting from VBT currently not supported on this platform
backlight frequency conversion failed
backlight frequency %u Hz from VBT
clamping VBT min backlight %d/255 to %d/255
cpu backlight was enabled, disabling
pch backlight already enabled
updating intel_backlight, brightness=%d/%d
Failed to register backlight: %ld
Connector %s backlight sysfs interface registered
no backlight present per VBT, but present per quirk
failed to setup backlight for connector %s
Connector %s backlight initialized, %s, brightness %u/%u
Skipping backlight disable on vga switch
cpu backlight already enabled
drivers/gpu/drm/i915/intel_sdvo.c initialising analog device %d
connector_is_digital? %d, monitor_is_digital? %d
h_overscan: max %d, default %d, current %d
v_overscan: max %d, default %d, current %d
hpos: max %d, default %d, current %d
vpos: max %d, default %d, current %d
saturation: max %d, default %d, current %d
contrast: max %d, default %d, current %d
hue: max %d, default %d, current %d
sharpness: max %d, default %d, current %d
brightness: max %d, default %d, current %d
flicker_filter: max %d, default %d, current %d
flicker_filter_adaptive: max %d, default %d, current %d
flicker_filter_2d: max %d, default %d, current %d
tv_chroma_filter: max %d, default %d, current %d
tv_luma_filter: max %d, default %d, current %d
SDVO capabilities:
vendor_id: %d
device_id: %d
device_rev_id: %d
sdvo_version_major: %d
sdvo_version_minor: %d
sdvo_inputs_mask: %d
smooth_scaling: %d
sharp_scaling: %d
up_scaling: %d
down_scaling: %d
stall_support: %d
output_flags: %d
%s: Unknown SDVO output type (0x%02x%02x)
SDVO output failed to setup on %s
%s device VID/DID: %02X:%02X.%02X, clock range %dMHz - %dMHz, input 1: %c, input 2: %c, output 1: %c, output 2: %c
SDVO pixel multiplier mismatch, port: %i, encoder: %i
First %s output reported failure to sync
SDVO TV clock out of range: %i
writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i
<6>[drm] Setting output timings on %s failed
<6>[drm] Setting input timings on %s failed
unknown pixel multiplier specified
SDVO_CMD_GET_ATTACHED_DISPLAYS SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE SDVO_CMD_GET_INPUT_TIMINGS_PART1 SDVO_CMD_GET_INPUT_TIMINGS_PART2 SDVO_CMD_SET_INPUT_TIMINGS_PART1 SDVO_CMD_SET_INPUT_TIMINGS_PART2 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1 SDVO_CMD_SET_OUTPUT_TIMINGS_PART2 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1 SDVO_CMD_GET_OUTPUT_TIMINGS_PART2 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS SDVO_CMD_GET_SUPPORTED_TV_FORMATS SDVO_CMD_GET_SUPPORTED_POWER_STATES SDVO_CMD_SET_ENCODER_POWER_STATE SDVO_CMD_SET_DISPLAY_POWER_STATE SDVO_CMD_SET_CONTROL_BUS_SWITCH SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS SDVO_CMD_GET_MAX_FLICKER_FILTER SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE SDVO_CMD_GET_MAX_FLICKER_FILTER_2D SDVO_CMD_GET_FLICKER_FILTER_2D SDVO_CMD_SET_FLICKER_FILTER_2D SDVO_CMD_GET_MAX_TV_CHROMA_FILTER SDVO_CMD_GET_MAX_TV_LUMA_FILTER SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER Detected Composite TV connection
Detected S-Video TV connection
Detected Component TV connection
Integrated TV is not present.
<6>[drm] VGT interface version mismatch!
<6>[drm] Virtual GPU for Intel GVT-g detected.
<6>[drm] balloon space: range [ 0x%lx - 0x%lx ] %lu KiB.
<6>[drm] VGT ballooning configuration:
<6>[drm] Mappable graphic memory: base 0x%lx size %ldKiB
<6>[drm] Unmappable graphic memory: base 0x%lx size %ldKiB
Invalid ballooning configuration!
<6>[drm] VGT balloon successfully
unregister_oom_notifier(&dev_priv->mm.oom_notifier) drivers/gpu/drm/i915/i915_dma.c &dev_priv->modeset_restore_lock i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags=%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s <6>[drm] This is an early pre-production Haswell machine. It may not be fully functional.
failed to remove conflicting framebuffer drivers
Failed to create our workqueue.
Failed to create our dp workqueue.
Failed to create our hangcheck workqueue.
<6>[drm] Display disabled (module parameter)
<6>[drm] Display fused off, disabling
has subslice power gating: %s
<6>[drm] failed to find VBIOS tables
timeout disabling GT waking
!HAS_RUNTIME_PM(dev) WARN_ON_ONCE(%s) Resuming device
Device resumed
KMS and UMS disabled.
Failed to reset chip: %i
Failed hw init on reset %d
Found Ibex Peak PCH
!IS_GEN5(dev) WARN_ON(%s) Found CougarPoint PCH
Found PantherPoint PCH
Found LynxPoint PCH
Found LynxPoint LP PCH
Found SunrisePoint PCH
!IS_SKYLAKE(dev) Found SunrisePoint LP PCH
Assuming Ibex Peak PCH
Assuming CouarPoint PCH
Assuming LynxPoint PCH
Assuming SunrisePoint PCH
No PCH found.
off Suspending device
Device suspended
Suspend complete failed: %d
dev: %p
i915 Intel Graphics 20151010 &dev_priv->pm_qos spurious interrupt
CRC buffer overflowing
I915_READ(SDEIER) != 0 WARN_ON(%s) !intel_irqs_enabled(dev_priv) bits & ~mask WARN_ON_ONCE(%s) dev_priv->rps.pm_iir Audio CP request interrupt
Audio CP change interrupt
pipe %c FDI IIR: 0x%08x
PCH poison interrupt
Poison interrupt
PCH HDCP audio interrupt
Unexpected DE Misc interrupt
Unexpected DE Port interrupt
!mode->crtc_clock Invalid crtc %u
crtc %u is disabled
L3_PARITY_ERROR=1 ROW=%d BANK=%d SUBBANK=%d SLICE=%d ERROR=1 RESET=1 ERROR=0 resetting chip
<3>i915: IPEIR: 0x%08x
<3>i915: IPEHR: 0x%08x
<3>i915: INSTPS: 0x%08x
<3>i915: ACTHD: 0x%08x
<3>i915: page table error
<3>i915: PGTBL_ER: 0x%08x
<3>i915: instruction error
<3>i915: INSTPM: 0x%08x
EIR stuck: 0x%08x, masking
Kicking stuck wait on %s Kicking stuck semaphore on %s no progress stuck <6>[drm] %s on %s
Ring hung %x
%u
%d
Resetting error state
l3 parity sysfs setup failed
RPS sysfs setup failed
error l3_parity_slice_1 l3_parity gt_RP0_freq_mhz gt_RP1_freq_mhz gt_RPn_freq_mhz gt_act_freq_mhz gt_cur_freq_mhz gt_max_freq_mhz gt_min_freq_mhz vlv_rpe_freq_mhz rc6_enable rc6_residency_ms rc6p_residency_ms rc6pp_residency_ms media_rc6_residency_ms i915/skl_dmc_ver1.bin i915/bxt_dmc_ver1.bin Loading %s
Finished loading %s
CSR is not loaded.
CSR SSP Base Not fine
CSR HTP Not fine
&dev_priv->rps.hw_lock Latency value missing
off on Enabling RC6 states: RC6 %s
A B FIFO size - (0x%08x) %s: %d
FIFO watermark level: %ld
plane->wm.fifo_size != 63 WARN_ON(%s) fifo_size != 512 - 1 flush pipe %c (pass %d)
primary sprite Pipe %c %s %c FIFO size: %d
disabled enabled memory self-refresh is %s
val > dev_priv->rps.max_freq val < dev_priv->rps.min_freq Odd GPU freq value
%s WM%d latency not provided
GPLL not enabled
no yes GPLL enabled? %s
GPU status: 0x%08x
<6>[drm] RC6 %s
SKL Mailbox read error = %d
DSPFW1 register is %x
DSPFW3 register is %x
self-refresh entries: %d
fifo_left != 0 htotal == 0 level == 0 && wm > max_wm p->pixel_rate == 0 WARN_ON(!wm_changed)
wm_lp != 1 !r->enable bad pxval: %ld
!dev_priv->vlv_pctx include/drm/drm_gem.h PCBR: 0x%08x
DDR speed: %d MHz
max GPU freq: %d MHz (%u)
RPe GPU freq: %d MHz (%u)
min GPU freq: %d MHz (%u)
Odd GPU freq values
ips_link_to_i915_driver include/drm/drm_backport.h unknown fsb frequency 0x%04x
Gen9 Plane Primary Sprite Cursor 2 3 SR latency is 0, disabling
Device still suspended.
WARN_ON(%s) !power_well->count disabling %s
enabling %s
Initial PHY_CONTROL=0x%08x
Interrupts not disabled yet.
DC5 still not disabled.
Disabling DC9
Power well on.
Enabling DC9
&power_domains->lock ctrl != state ctrl << 16 != state WARN_ON_ONCE(%s) power_well->data != PIPE_A PG0 not enabled
PG1 in disabled state
Unknown power well %lu
Disabling DC6
Enabling %s
%s enable timeout
Disabling %s
CSR firmware not ready (%d)
Runtime PM not enabled.
Backlight is not disabled.
Enabling DC6
Enabling DC5
Enabling power well
Timeout enabling power well
always-on display power well 1 MISC IO power well power well 2 DDI A/E power well DDI B power well DDI C power well DDI D power well dpio-common-bc dpio-common-d dpio-tx-b-01 dpio-tx-b-23 dpio-tx-c-01 dpio-tx-c-23 dpio-common i915_dpcd size > sizeof(buf) WARN_ON(%s) %04x: %*ph
%c %s
no yes LLC: %s
eLLC: %zuMB
Current sequence (%s): %x
gen: %d
pch: %d
is_mobile: %s
is_i85x: %s
is_i915g: %s
is_i945gm: %s
is_g33: %s
need_gfx_hws: %s
is_g4x: %s
is_pineview: %s
is_broadwater: %s
is_crestline: %s
is_ivybridge: %s
is_valleyview: %s
is_haswell: %s
is_skylake: %s
is_preliminary: %s
has_fbc: %s
has_pipe_cxsr: %s
has_hotplug: %s
cursor_needs_physical: %s
has_overlay: %s
overlay_needs_physical: %s
supports_tv: %s
has_llc: %s
has_ddi: %s
has_fpga_dbg: %s
1 0 %02lx %lx not supported
GPU idle: %s
IRQs disabled: %s
Usage count: %d
no ppgtt for context %d
default context:
context %d:
Copied %d bytes from user
Got %d for test active
%llu
0x%llx
0x%08llx
Use count Power well/domain %-25s %s
%-25s %d
PIPE_A PIPE_B PIPE_C PIPE_A_PANEL_FITTER PIPE_B_PANEL_FITTER PIPE_C_PANEL_FITTER TRANSCODER_A TRANSCODER_B TRANSCODER_C TRANSCODER_EDP PORT_DDI_A_2_LANES PORT_DDI_A_4_LANES PORT_DDI_B_2_LANES PORT_DDI_B_4_LANES PORT_DDI_C_2_LANES PORT_DDI_C_4_LANES PORT_DDI_D_2_LANES PORT_DDI_D_4_LANES PORT_DDI_E_2_LANES PORT_DSI PORT_CRT PORT_OTHER VGA AUDIO PLLS AUX_A AUX_B AUX_C AUX_D GMBUS INIT %-23s %d
WM%d %u (%u.%u usec)
nonexisting DP port %c
Size End Start %-15s%8s%8s%8s
Pipe %c
Plane%-8d%8u%8u%8u
Cursor %-13s%8u%8u%8u
DPLL%i: %s, id: %i
tracked hardware state:
dpll: 0x%08x
dpll_md: 0x%08x
fp0: 0x%08x
fp1: 0x%08x
wrpll: 0x%08x
CRTC %d: eDP:
DSI:
HDMI:
DP:
Other encoder (id=%d).
VBT: DRRS_type: Static VBT: DRRS_type: Seamless VBT: DRRS_type: None
DRRS Supported: Yes
Idleness DRRS: Disabled Busy_frontbuffer_bits: 0x%X
DRRS_State: DRRS_HIGH_RR
DRRS_State: DRRS_LOW_RR
DRRS_State: Unknown(%d)
Vrefresh: %d DRRS Supported : No
No active crtc found
pipe unknown object %s
unknown pipe %s
unknown source %s
!IS_G4X(dev) stopping CRCs for pipe %c
Stopping rings 0x%08llx
Resetting error state
Dropping caches: 0x%08llx
Workarounds applied: %d
OK FAIL %llu bug DDC = 0x%08x
DDC2 = 0x%08x
C0DRB3 = 0x%04x
C1DRB3 = 0x%04x
MAD_DIMM_C0 = 0x%08x
MAD_DIMM_C1 = 0x%08x
MAD_DIMM_C2 = 0x%08x
TILECTL = 0x%08x
GAMTARBMODE = 0x%08x
ARB_MODE = 0x%08x
DISP_ARB_CTL = 0x%08x
L-shaped memory detected
enabled disabled self-refresh: %s
Currently: unknown
Currently: enabled
Currently: disabled
RPS enabled? %d
GPU busy? %d
CPU waiting? %d
, active %s [%d]: %d boosts%s
Semaphore boosts: %d%s
MMIO flip boosts: %d%s
Kernel boosts: %d
GuC total action count: %llu
GuC action failure count: %u
GuC last action status: 0x%x
GuC submissions:
Total %s: %llu
GuC execbuf client @ %p:
Failed to queue: %u
Failed doorbell: %u
Last submission result: %d
Submissions: %llu %s
Total: %llu
Display IER: %08x
Display IIR: %08x
Display IIR_RW: %08x
Display IMR: %08x
Pipe %c stat: %08x
Port hotplug: %08x
DPFLIPSTAT: %08x
DPINVGTT: %08x
GT Interrupt IMR %d: %08x
GT Interrupt IIR %d: %08x
GT Interrupt IER %d: %08x
PCU interrupt mask: %08x
PCU interrupt identity: %08x
PCU interrupt enable: %08x
Pipe %c power disabled
Pipe %c IMR: %08x
Pipe %c IIR: %08x
Pipe %c IER: %08x
Master IER: %08x
Render IER: %08x
Render IIR: %08x
Render IMR: %08x
PM IER: %08x
PM IIR: %08x
PM IMR: %08x
Interrupt enable: %08x
Interrupt identity: %08x
Interrupt mask: %08x
Pipe %c stat: %08x
%s requests: %d
%x @ %d: %s [%d]
No requests
SSEU Device Info
Available Slice Total: %u
Available EU Total: %u
Has Slice Power Gating: %s
Has EU Power Gating: %s
SSEU Device Status
Enabled Slice Total: %u
Enabled Subslice Total: %u
Enabled EU Total: %u
Semaphores are disabled
%s
Last signal: 0x%08llx (0x%02llx) Last wait: 0x%08x
Sync seqno:
0x%08x %02x%02x%02x%02x%02x%02x
PSR not supported
Sink_Support: %s
Source_OK: %s
Enabled: %s
Active: %s
Re-enable work scheduled: %s
HW Enabled & Active bit: %s pipe %c Performance_Counter: %u
PDP%d 0x%016llx
GFX_MODE: 0x%08x
PP_DIR_BASE: 0x%08x
PP_DIR_BASE_READ: 0x%08x
PP_DIR_DCLV: 0x%08x
aliasing PPGTT:
pd gtt offset: 0x%08x
ECOCHK: 0x%08x
proc: %s
%s.wake_count = %u
Status pointer: 0x%08X
%d requests in queue
Head request id: %u
Head request tail: %u
[k]batch pool g p * %x purgeable dirty ] %x %x%s%s%s (name: %d) (pinned x %d) (display) (fence: %d) pp , type: %u) ) (stolen: %08llx) (%s mappable) (%s) (frontbuffer: 0x%03x) HW context (default context %s) %s: %s cache[%d]: %d objects
total: %d
Total fences = %d
unused Active:
Inactive:
FBC enabled
FBC disabled: %s
Compressing: %s
unsupported on this chipset
%d %d %d
GMCH temp: %ld
Chipset power: %ld
GFX power: %ld
Total power: %ld
Video Turbo Mode: %s
Turbo enabled: %s
HW control enabled: %s
SW control enabled: %s
RC6 Enabled: %s
Down Up Render Power Well: %s
Media Power Well: %s
RC information accurate: %s
RC1e Enabled: %s
Deep RC6 Enabled: %s
Deepest RC6 Enabled: %s
Current RC state: Core Power Down
on
RC3
RC6
RC7
Unknown
Core Power Down: %s
RC6 residency since boot: %u
RC6 voltage: %dmV
RC6+ voltage: %dmV
RC6++ voltage: %dmV
HD boost: %s
Boost freq: %d
Gated voltage change: %s
Starting frequency: P%d
Max P-state: P%d
Min P-state: P%d
RS1 VID: %d
RS2 VID: %d
Render standby enabled: %s
Current RS state: RC1
RC1E
RS1
RS2 (RC6)
RC3 (RC6+)
unknown
Hangcheck disabled
Hangcheck inactive
%s:
seqno = %x [current %x]
max ACTHD = 0x%08llx
score = %d
action = %d
Requested P-state: %d
Requested VID: %d
Current VID: %d
Current P-state: %d
GT_PERF_STATUS: 0x%08x
Render p-state ratio: %d
Render p-state VID: %d
Render p-state limit: %d
RPSTAT1: 0x%08x
RPMODECTL: 0x%08x
RPINCLIMIT: 0x%08x
RPDECLIMIT: 0x%08x
RPNSWREQ: %dMHz
CAGF: %dMHz
RP CUR UP EI: %dus
RP CUR UP: %dus
RP PREV UP: %dus
Up threshold: %d%%
RP CUR DOWN EI: %dus
RP CUR DOWN: %dus
RP PREV DOWN: %dus
Down threshold: %d%%
Current freq: %d MHz
Actual freq: %d MHz
Idle freq: %d MHz
Min freq: %d MHz
Max freq: %d MHz
DDR freq: %d MHz
actual GPU freq: %d MHz
current GPU freq: %d MHz
max GPU freq: %d MHz
min GPU freq: %d MHz
idle GPU freq: %d MHz
no P-state info available
GuC firmware status:
path: %s
fetch: %s
load: %s
version wanted: %d.%d
version found: %d.%d
GuC status 0x%08x:
Bootrom status = 0x%x
uKernel status = 0x%x
MIA Core status = 0x%x
Scratch registers:
%2d: 0x%x
Stall check enabled, %d prepares
MMIO update completed? %d
Stolen:
%u objects, %zu bytes
%llu [%llu] gtt total
i915_forcewake_user %8u %8x %8x %8x %8x %8x
fixed mode:
CRTC info
---------
primary plane disabled
, mode:
Connector info
--------------
name: %s
subpixel order: %s
CEA rev: %d
DPCD rev: %x
audio support: %s
modes:
0x%08x 0x%08x 0x%08x 0x%08x
CONTEXT: %s %u
Not bound in GGTT
page == NULL i915_capabilities i915_gem_objects i915_gem_gtt i915_gem_pinned i915_gem_active i915_gem_inactive i915_gem_stolen i915_gem_pageflip i915_gem_request i915_gem_seqno i915_gem_fence_regs i915_gem_interrupt i915_gem_hws i915_gem_hws_blt i915_gem_hws_bsd i915_gem_hws_vebox i915_gem_batch_pool i915_guc_info i915_guc_load_status i915_guc_log_dump i915_frequency_info i915_hangcheck_info i915_drpc_info i915_emon_status i915_ring_freq_table i915_frontbuffer_tracking i915_fbc_status i915_ips_status i915_sr_status i915_opregion i915_gem_framebuffer i915_context_status i915_dump_lrc i915_execlists i915_forcewake_domains i915_swizzle_info i915_ppgtt_info i915_llc i915_edp_psr_status i915_sink_crc_eDP1 i915_energy_uJ i915_runtime_pm_status i915_power_domain_info i915_display_info i915_semaphore_status i915_shared_dplls_info i915_dp_mst_info i915_wa_registers i915_ddb_info i915_sseu_status i915_drrs_status i915_rps_boost_info i915_pipe_A_crc i915_pipe_B_crc i915_pipe_C_crc i915_wedged i915_max_freq i915_min_freq i915_cache_sharing i915_ring_stop i915_ring_missed_irq i915_ring_test_irq i915_gem_drop_caches i915_error_state i915_next_seqno i915_display_crc_ctl i915_pri_wm_latency i915_spr_wm_latency i915_cur_wm_latency i915_fbc_false_color i915_dp_test_data i915_dp_test_type i915_dp_test_active none plane1 plane2 pf TV DP-B DP-C DP-D auto X Y bit9 bit9/bit10 bit9/bit11 bit9/bit10/bit11 unknown bit9/bit17 bit9/bit10/bit17 Failed to vmap pages
WARN_ON(%s) CMD: Failed to vmap batch
CMD: Failed to copy batch
!hash_empty(ring->cmd_hash) CMD: cmd_parser_init failed!
WARN_ON(%s) include/drm/drm_gem.h i915.enable_execlists WARN_ON(%s) L3 remapping failed
ring init context: %d
HW context %d destroyed
ret include/drm/drm_gem.h Couldn't pin %d
PPGTT setup failed (%ld)
HW context %d created
LR fake HW i915 WARN_ON(%s) !list_empty(&vm->active_list) i915_vma_unbind(vma) !list_empty(&vma->exec_list) include/drm/drm_gem.h WARN_ON(%s) Failed to lookup VMA
include/drm/drm_gem.h %s didn't clear reload
no rel constants on pre-gen4
sol reset is gen7/rcs only
execbuf with %d buffers
RS is not available on %s
Could not create LRC %u: %d
execbuf2 with %d buffers
dirty rvsd2 field
WARN_ON(%s) !obj->map_and_fenceable fence->pin_count flags == 0 WARN_ON(%s) P G !view GMADR size = %lldM
GTT stolen size = %zdM
ppgtt mode: %i
Scratch setup failed
Unknown GMADR size (%llx)
!p->page failed to set up gmch
px_dma(vm->scratch_page) == 0 !pdp !pdp->page_directory[pdpe] !pd->page_table[pde] !px_page(pt) PDE: %x
0x%lx [%03d,%04d]: = %08x SCRATCH
PDPE #%d
0x%llx [%03d,%03d,%04d]: = %llx PML4E #%llu
!pdp->page_directory[i] !pd->page_table[i] !ppgtt->pml4.pdps[i] !bitmap_empty(new_pds, pdpes) Couldn't idle GPU
PPGTT GGTT !USES_FULL_48BIT_PPGTT(dev) Adding PPGTT at offset %x
i915_gem_obj_ggtt_bound(obj) Reservation failed: %i
include/drm/drm_mm.h start + length < start start + length > vm->total pt == vm->scratch_pt !pd !pt !pd_len WARN_ON(%s) ppgtt global include/drm/drm_gem.h
i915_gem_object i915_gem_vma i915_gem_request &dev_priv->fb_tracking.lock vma->node.allocated include/linux/scatterlist.h !ctx request == NULL emit|add_request failed: %d!
IRQs disabled *timeout < 0 !ring->irq_get(ring) no view specified include/drm/drm_backport.h vma->pin_count == 0 obj->pin_display == 0 ret != -EIO bytes != size !to_req PPGTT enable HW failed %d
(ignored) !ring->default_context allow wake ack timed out
dev_priv->mm.busy ret == -ERESTARTSYS i915_vma_unbind(vma) obj->frontbuffer_bits obj->pages_pin_count ggtt !ggtt_view mappable total include/drm/drm_gem.h ring->id != RCS WARN_ON(%s) only %d relocs resolved
include/drm/drm_gem.h offset=0x%x, size=%d
&dev_priv->mm.stolen_lock Graphics Stolen Memory WARN_ON(%s) size == 0 size & 4095 stolen_offset & 4095 include/drm/drm_gem.h unknown tiling mode
include/drm/drm_gem.h include/drm/drm_backport.h &dev_priv->mm_lock include/linux/scatterlist.h obj->userptr.mm == NULL WARN_ON(%s) include/drm/drm_backport.h include/drm/drm_gem.h ret && ret != -EIO L3+LLC uncached snooped LLC WT WARN_ON(%s) overflow %s [%d]:
%02x ] %02x P p dirty purgeable userptr (name: %d) (fence: %d)
%08x : %08x
no error state collected
%s
Time: %ld s %ld us
Reset count: %u
Suspend count: %u
PCI ID: 0x%04x
IOMMU enabled?: %d
EIR: 0x%08x
IER: 0x%08x
GTIER gt %d: 0x%08x
GTIER: 0x%08x
PGTBL_ER: 0x%08x
FORCEWAKE: 0x%08x
DERRMR: 0x%08x
CCID: 0x%08x
Missed interrupts: 0x%08lx
fence[%d] = %08llx
INSTDONE_%d: 0x%08x
ERROR: 0x%08x
DONE_REG: 0x%08x
ERR_INT: 0x%08x
%s command stream:
START: 0x%08x
HEAD: 0x%08x
TAIL: 0x%08x
CTL: 0x%08x
HWS: 0x%08x
ACTHD: 0x%08x %08x
IPEIR: 0x%08x
IPEHR: 0x%08x
INSTDONE: 0x%08x
BBADDR: 0x%08x %08x
BB_STATE: 0x%08x
INSTPS: 0x%08x
INSTPM: 0x%08x
FADDR: 0x%08x %08x
RC PSMI: 0x%08x
FAULT_REG: 0x%08x
GFX_MODE: 0x%08x
PDP%d: 0x%016llx
PP_DIR_BASE: 0x%08x
seqno: 0x%08x
no yes waiting: %s
ring->head: 0x%08x
ring->tail: 0x%08x
unknown hangcheck: %s [%d]
vm[%d]
Active Pinned (submitted by %s [%d]) %s --- %d requests
%s --- ringbuffer = 0x%08x
%s --- HW Status = 0x%08llx
[%04x] %08x %08x %08x %08x
%s --- HW Context = 0x%08x
Semaphore page = 0x%08x
GPU HANG: ecode %d:%d:0x%08x , in %s [%d] continue reset , reason: %s, action: %s <6>[drm] %s
render bsd blt vebox bsd2 X Y idle wait active active (loop) kick hung 1 WARN_ON_ONCE(%s) i915_pipe_update_start %s: i915_pipe_update_end i915_gem_object_create obj=%p, size=%u
i915_gem_shrink dev=%d, target=%lu, flags=%x
i915_vma_bind , mappable i915_vma_unbind i915_va_alloc vm=%p (%s), 0x%llx-0x%llx
i915_page_table_entry_alloc i915_page_table_entry_map i915_gem_object_change_domain i915_gem_object_pwrite obj=%p, offset=%u, len=%u
i915_gem_object_pread i915_gem_object_fault , writable CPU GTT obj=%p, %s index=%u %s
obj=%p
i915_gem_object_clflush i915_gem_object_destroy i915_gem_evict dev=%d, size=%d, align=%d %s
i915_gem_evict_everything dev=%d
i915_gem_evict_vm dev=%d, vm=%p
i915_gem_ring_sync_to i915_gem_ring_dispatch i915_gem_ring_flush dev=%u, ring=%u, seqno=%u
i915_gem_request_add i915_gem_request_retire i915_gem_request_complete i915_gem_request_wait_end i915_gem_request_notify i915_gem_request_wait_begin no yes (NB) i915_flip_request plane=%d, obj=%p
i915_flip_complete intel_gpu_freq_change new_freq=%u
dev=%u, vm=%p
i915_ppgtt_create i915_ppgtt_release dev=%u, ctx=%p, ctx_vm=%p
i915_context_create i915_context_free switch_mm pipe enum pipe frame u32 scanline min max obj struct drm_i915_gem_object * size dev int target unsigned long flags unsigned vm struct i915_address_space * offset u64 start end name __data_loc char[] px pde first last cur_ptes read_domains write_domain len index gtt bool write align sync_from sync_to seqno ring invalidate flush blocking plane freq ctx struct intel_context * to %*pb WARN_ON(%s) i915 WARN_ON(%s) i915.enable_ppgtt == -1 lrca & 0xFFFFFFFF00000FFFULL !intel_irqs_enabled(dev_priv) Never submitted head request
req == NULL ringbuf->reserved_in_use include/drm/drm_gem.h ctx->engine[ring->id].state Could not set to CPU domain
Could not get object pages
Failed to populate LRC: %d
ring create req: %d
ring init context: %d
w->count == 0 WARN_ON_ONCE(%s) Execlists enabled for %s
req1 && req1->elsp_submitted sol reset is gen7 only
render ring ring->id != RCS bsd ring blitter ring video enhancement ring bds2 ring WARN_ON(%s) !ringbuf->reserved_in_use WARN_ON(%s) ringbuf->reserved_in_use ringbuf->reserved_size idx >= I915_MAX_WA_REGS include/drm/drm_gem.h !intel_irqs_enabled(dev_priv) req == NULL ring->id != RCS ring->scratch.obj ring->buffer %s hws offset: 0x%08x
video enhancement ring blitter ring bsd2 ring bsd ring init render state: %d
render ring !dev_priv->semaphore_obj Failed to allocate batch bo
Failed to ping batch bo
Device suspended
GT wake FIFO error 0x%x
WARN_ON(%s) writing to reading after before domain->wake_count id unknown d->wake_count d->reg_set == 0 domain->wake_count == 0 dev_priv->pm.suspended !fw_domains active_domains %s: reset request timeout
<6>[drm] Found %zuMB of eLLC
render blitter media UNKNOWN! i915/skl_guc_ver4.bin include/drm/drm_gem.h returning %d
GuC fw fetch status %s
set-domain failed %d
pin failed %d
GUC: unsupported core family
SUCCESS FAIL NONE PENDING len < 1 || len > 15 WARN_ON(%s) include/drm/drm_gem.h desc.engines_used == 0 (value & GEN8_DRB_VALID) != 0 wq_off & 3 normal high acomp->ops || acomp->dev WARN_ON(%s) Disable audio codec
ELD size %d
%s: crtc is NULL
no pipe for the port %c
pipe %c connects port %c
port == PORT_A !HAS_DDI(dev_priv) WARN_ON_ONCE(%s) invalid port: %d
no suitable N value is found
WARN_ON(%s) CRTC PLANE *scaler_id < 0 Cannot find scaler for %s:%d
Unknown plane property '%s'
!drm_crtc_state WARN_ON(%s) VBT header incomplete
$VBT VBT invalid signature
BDB header incomplete
BDB incomplete
Using VBT from %s: %20s
Set default to SSC at %d kHz
OpRegion PCI ROM crt_ddc_bus_pin: %d
VBT initial LVDS value %x
high low Incorrect SDVO port. Skip it
SDVOB SDVOC Found MIPI as LFP
DRRS State Enabled:%d
No PSR BDB found.
No MIPI config BDB found Found MIPI sequence block
Found mipi sequence - %d
undefined sequence
Unknown element
Port %c is analog
Port %c is TMDS compatible
Port %c is internal DP
ThinkCentre A57 Num Pipes: %d
PWR_WELL_CTL2: %08x
Pipe [%d]:
off on Power: %s
SRC: %08x
STAT: %08x
Plane [%d]:
CNTR: %08x
STRIDE: %08x
SIZE: %08x
POS: %08x
ADDR: %08x
SURF: %08x
TILEOFF: %08x
Cursor [%d]:
BASE: %08x
CPU transcoder: %c
CONF: %08x
HTOTAL: %08x
HBLANK: %08x
HSYNC: %08x
VTOTAL: %08x
VBLANK: %08x
VSYNC: %08x
Unsupported divider value
failed to read control word
failed to write control word
HPLL VCO %u kHz
enabling CxSR downclocking
disabling CxSR downclocking
Max CD clock rate: %d kHz
Max dotclock rate: %d kHz
num_connectors == 0 WARN_ON(%s) Unknown cd freq selection
!crtc_state->base.state dis en %sabling fdi C rx
for crtc_state = %p
!target_freq WARN_ON_ONCE(%s) !encoder->crtc was_visible visible !HAS_DDI(dev) !HAS_PCH_SPLIT(dev) !ctx !state cpu_transcoder: %c
pipe bpp: %i, dithering: %i
audio: %i, infoframes: %i
requested mode:
adjusted mode:
port clock: %d
pipe src size: %dx%d
disabled enabled ips: %i
double wide: %i
planes on this crtc
STANDARD CURSOR Incorrect port type
FDI_RX_IIR 0x%x
FDI train 1 done, level %i.
FDI train 2 done, level %i.
FDI train done.
FDI train 1 done.
FDI train 1 fail!
FDI train 2 done.
FDI train 2 fail!
FDI train done
HAS_DDI(dev) pll->active == 0 !pll->on disabling %s
pll == NULL pll->config.crtc_mask == 0 pll->on enabling %s
Failed to write to D_COMP
invalid cdclk frequency
Switching to FCLK failed
unsupported CDCLK freq %d DBuf power disable timeout!
Display already initialized
DBuf power enable timeout!
DPLL %d failed to lock
DBuf power disable timeout
Couldn't disable DPLL0
%s change in progress
cdclk failed to alloc fb
obj == NULL PLL %d failed to lock
buffer is too small
cursor cannot be tiled
No Y tiling for legacy addfb
Unsupported tiling 0x%llx!
linear tiled unsupported pixel format: %s
framebuffer init failed %d
no such CRTC id
!in_interrupt() Changing CDCLK to %dKHz
DBuf power enable timeout
DPLL0 not locked
shared_dpll[i].crtc_mask !encoder CRTC:%d allocated %s
using %s for pipe %c
Unexpected PCH type %d
Removing stuck page flip
ret x != src_x || y != src_y !dst_w || !dst_h intel_fb_obj(old_fb) == NULL include/drm/drm_backport.h failed to attach phys object
disabling pipe %c
pipe_off wait timed out
enabling pipe %c
intel_crtc->active !pll->config.crtc_mask setting up %s
!state->allow_modeset [CONNECTOR:%d:%s]
[ENCODER:%d:%s]
[CRTC:%d]
pipe state doesn't match!
[hw state] [sw state] %s
pll hw state mismatch
LP PCH doesn't have FDI
Using SSC on panel
Using SSC on eDP
Disabling SSC entirely
Disabling package C8+
LCPLL not locked yet
Enabling package C8+
CRTC for pipe %c enabled
Power well on
<6>[drm] Power well on
SPLL enabled
<6>[drm] SPLL enabled
WRPLL1 enabled
<6>[drm] WRPLL1 enabled
WRPLL2 enabled
<6>[drm] WRPLL2 enabled
Panel power on
<6>[drm] Panel power on
CPU PWM1 enabled
<6>[drm] CPU PWM1 enabled
CPU PWM2 enabled
<6>[drm] CPU PWM2 enabled
PCH PWM1 enabled
<6>[drm] PCH PWM1 enabled
Utility pin enabled
<6>[drm] Utility pin enabled
PCH GTC enabled
<6>[drm] PCH GTC enabled
IRQs enabled
<6>[drm] IRQs enabled
LCPLL still locked
include/drm/drm_gem.h Encoder config failure
CRTC fixup failed
[fastset] [modeset] include/drm/drm_crtc.h !connector_state->crtc crtc->active [setup_hw_state] put_domains intel fb init failed
initial plane fb obj %p
&dev_priv->pps_mutex s %d display pipe%s available.
czclk CZ clock rate: %d kHz
probing SDVOB
probing HDMI on SDVOB
probing SDVOC
probing HDMI on SDVOC
NCR Corporation PCH DPLL A PCH DPLL B &dev_priv->fbc.lock FBC idle timed out
disabled FBC
enabled fbc on plane %c
unsupported by this chipset no output not enough stolen memory FBC unsupported on plane more than one pipe active disabled per module param disabled per chip default rotation unsupported Kernel debugger is active pixel rate is too big pixel format is invalid unknown reason Disabling FBC: %s
WARN_ON(%s) stride < 512 (stride & (64 - 1)) != 0 <6>[drm] pipe %c underrun
WARN_ON(%s) WARN_ON(%s) short long digital hpd port %c - %s
Broadcast RGB audio Automatic Full Limited 16:235 force-dvi off auto on Register file at 0x%08lx:
OBUF_0Y: 0x%08x
OBUF_1Y: 0x%08x
OBUF_0U: 0x%08x
OBUF_0V: 0x%08x
OBUF_1U: 0x%08x
OBUF_1V: 0x%08x
OSTRIDE: 0x%08x
YRGB_VPH: 0x%08x
UV_VPH: 0x%08x
HORZ_PH: 0x%08x
INIT_PHS: 0x%08x
DWINPOS: 0x%08x
DWINSZ: 0x%08x
SWIDTH: 0x%08x
SWIDTHSW: 0x%08x
SHEIGHT: 0x%08x
YRGBSCALE: 0x%08x
UVSCALE: 0x%08x
OCLRC0: 0x%08x
OCLRC1: 0x%08x
DCLRKV: 0x%08x
DCLRKM: 0x%08x
SCLRKVH: 0x%08x
SCLRKVL: 0x%08x
SCLRKEN: 0x%08x
OCONFIG: 0x%08x
OCMD: 0x%08x
OSTART_0Y: 0x%08x
OSTART_1Y: 0x%08x
OSTART_0U: 0x%08x
OSTART_0V: 0x%08x
OSTART_1U: 0x%08x
OSTART_1V: 0x%08x
OTILEOFF_0Y: 0x%08x
OTILEOFF_1Y: 0x%08x
OTILEOFF_0U: 0x%08x
OTILEOFF_0V: 0x%08x
OTILEOFF_1U: 0x%08x
OTILEOFF_1V: 0x%08x
FASTHSCALE: 0x%08x
UVSCALEV: 0x%08x
dev_priv->overlay WARN_ON(%s) include/drm/drm_gem.h userspace bug: no overlay
!obj dev_priv->overlay->active include/drm/drm_backport.h overlay->last_flip_req !overlay->active overlay->active overlay underrun, DOVSTA: %x
&dev_priv->psr.lock WARN_ON(%s) dev_priv->psr.active !(val & EDP_PSR_ENABLE) PSR already in use
HSW ties PSR to DDI A (eDP)
PSR disable by flag
WARN_ON(%s) write read Wrong plane <-> crtc mapping
WARN_ON(%s) !can_scale _DSM failed to evaluate _DSM: %d
MUX info connectors: %lld
Connector id: 0x%016llx
bad type port id: %s
display mux info: %s
aux/dc mux info: %s
hpd mux info: %s
Reserved Analog VGA LVDS HDMI/DVI_B HDMI/DVI_C HDMI/DVI_D DisplayPort_A DisplayPort_B DisplayPort_C DisplayPort_D WiDi unknown No MUX, iGPU only No MUX, dGPU only MUXed between iGPU and dGPU SWSCI request timed out
SWSCI request error %u
ACPI OpRegion not supported!
IntelGraphicsMem opregion signature mismatch
SWSCI supported
ASLE supported
Illum is not supported
bclp = 0x%08x
Pfit is not supported
PWM freq is not supported
SROT is not supported
ISCT is not supported
video WARN_ON(%s) No ACPI video bus found
_ADR %d outputs detected
failed to restore crtc mode
state != FBINFO_STATE_RUNNING WARN_ON(%s) !encoder->crtc i Enabled: %i, detected: %i
pipe %c not active, skipping
failed to pin obj: %d
include/drm/drm_gem.h !intel_fb->obj re-using BIOS fb
CH7017_LVDS_CONTROL_2: %02x
CH7017_OUTPUTS_ENABLE: %02x
CH7017_LVDS_POWER_DOWN: %02x
Registers after mode setting
ch7018 ch7019 ch7017 %s detected on %s, addr %d
%02X: %02X CH7011 CH7010B CH7009A CH7009B CH7301 CH7XXX VR00: 0x%04x
VR01: 0x%04x
VR10: 0x%04x
VR30: 0x%04x
VR40: 0x%04x
VR80: 0x%04x
VR81: 0x%04x
VR82: 0x%04x
VR83: 0x%04x
VR84: 0x%04x
VR85: 0x%04x
VR86: 0x%04x
VR87: 0x%04x
VR88: 0x%04x
VR8E: 0x%04x
VR8F: 0x%04x
Resetting the IVCH registers
SIL164_FREQ_LO: 0x%02x
SIL164_FREQ_HI: 0x%02x
SIL164_REG8: 0x%02x
SIL164_REG9: 0x%02x
SIL164_REGC: 0x%02x
TFP410_REV: 0x%02X
TFP410_CTL1: 0x%02X
TFP410_CTL2: 0x%02X
TFP410_CTL3: 0x%02X
TFP410_USERCFG: 0x%02X
TFP410_DE_DLY: 0x%02X
TFP410_DE_CTL: 0x%02X
TFP410_DE_TOP: 0x%02X
TFP410_DE_CNT: 0x%02X%02X
TFP410_DE_LIN: 0x%02X%02X
TFP410_H_RES: 0x%02X%02X
TFP410_V_RES: 0x%02X%02X
crt adpa set to 0x%x
[CONNECTOR:%d:%s] force=%d
CRT detected via hotplug
CRT not detected via hotplug
starting load-detect on CRT
ACER ZGB DELL XPS 8700 Invalid I_boost value %u
bad wrpll refclk
WARN_ON(%s) FDI link training failed!
Invalid DDI encoder type %d
dpll != SKL_DPLL0 PLL %d not locked
DPLL %d not locked
timeout waiting for PHY1 GRC
WRPLL 1 WRPLL 2 SPLL LCPLL1 is disabled
CDCLK source is not LCPLL
LCPLL is disabled
Incorrect PDiv
Incorrect KDiv
best_clock.m1 != 2 Invalid VCO
bad spll freq
bad port clock sel
Unsupported link rate
dpll == DPLL_ID_PRIVATE DPLL 1 DPLL 2 DPLL 3 PORT PLL A PORT PLL B PORT PLL C
%d
can't find connector
failed to allocate vcpi
failed to update payload %d
Sink OUI: %02hx%02hx%02hx
Branch OUI: %02hx%02hx%02hx
Sink is MST capable
Sink is not MST capable
disable enable HAS_DDI(dev) WARN_ON(%s)
k >= DP_MAX_SUPPORTED_RATES len <= 0 !IS_VALLEYVIEW(dev) !is_edp(intel_dp) pipes == 0 intel_dp->want_panel_vdd Turning eDP port %c VDD off
dp pll off, should be on
eDP PLL enable for clock %d
dp pll on, should be off
Panel doesn't support DRRS
dev_priv->drrs.dp DRRS already enabled
Wait complete
eDP port %c VDD not forced on [CONNECTOR:%d:%s]
no scaling not supported
DRRS not supported.
Unsupported refreshrate type
Using signal levels %08x
Using vswing level %d
Using pre-emphasis level %d
common_len <= 0 failed to get link status
clock recovery OK
clock recovery not ok, reset failed to train DP, aborting
got esi %3ph
got esi2 %3ph
, %s%d source rates: %s
sink rates: %s
common rates: %s
DPCD: %*ph
Detected EDP PSR Panel.
not supported supported PSR2 %s on sink yes no LINK_TRAINING test requested
TEST_PATTERN test requested
EDID test requested
PHY_PATTERN test requested
Invalid test request '%02x'
DP eDP DPDDC-A DPDDC-B DPDDC-C DPDDC-D DPDDC-E registering %s bus for %s
&dev_priv->drrs.mutex VBT doesn't support DRRS
short long got hpd irq on port %c - %s
Wait for panel power cycle
Turning eDP port %c VDD on
Status 0x%08x Control 0x%08x
txsize > 20 rxsize > 20 Wait for panel power on
dp_reg & DP_PORT_EN Enabling DP audio on pipe %c
MODE_NO_DBLESCAN
no fixed mode
drm_mode_duplicate failed
no device found
DPI FIFOs are not empty
DSI LP not going Low
pipe %c
Starting MIPI sequence - %s
Burst mode target is not set
disabled enabled Eot %s
Clockstop %s
video command Mode %s
Dual link: NONE
Pixel Format %d
TLPX %d
LP RX Timeout 0x%x
Turnaround Timeout 0x%x
Init Count 0x%x
HS to LP Count 0x%x
LP Byte Clock %d
DBI BW Timer 0x%x
LP to HS Clock Count 0x%x
HS to LP Clock Count 0x%x
BTA %s
no dsi device for port %c
UNDEFINED MIPI_SEQ_ASSERT_RESET MIPI_SEQ_INIT_OTP MIPI_SEQ_DISPLAY_ON MIPI_SEQ_DISPLAY_OFF MIPI_SEQ_DEASSERT_RESET
DSI CLK Out of Range
dsi_calc_mnp failed
dsi pll div %08x, ctrl %08x
DSI PLL locked
DSI PLL lock failed
Invalid BPP(0)
Calculated pclk=%u
wrong P1 divisor
wrong m_seed programmed
[CONNECTOR:%d:%s]
sil164 ch7xxx ivch tfp410 ch7017 ns2501 WARN_ON(%s) unknown info frame type %d
!crtc->config->has_hdmi_sink [CONNECTOR:%d:%s]
Live status not up! IS_BROXTON(dev_priv) couldn't fill AVI infoframe
Integrated gfx Intel couldn't fill SPD infoframe
dis en WARN_ON(%s) &dev_priv->gmbus_mutex i915 gmbus %s dpb dpc misc dpd vga ssc panel no scaling not supported
[CONNECTOR:%d:%s]
disable LVDS for eDP support
LVDS is not present in VBT
using mode from VBT: using current (BIOS) mode: single dual Can't support LVDS on pipe A
Apple Mac Mini (Core series) MSI IM-945GSE-A Dell Studio Hybrid Dell OptiPlex FX170 AOpen Mini PC AOpen Mini PC MP915 AOpen i915GMm-HFS AOpen i45GMx-I Aopen i945GTt-VFA Clientron U800 Clientron E830 Asus EeeBox PC EB1007 Asus AT5NM10T-I Hewlett-Packard HP t5740 Hewlett-Packard t5745 Hewlett-Packard st5747 MSI Wind Box DC500 Gigabyte GA-D525TUD Supermicro X7SPA-H Fujitsu Esprimo Q900 Intel D410PT Intel D425KT Intel D510MO Intel D525MW Apple MacBook Pro 15" (2010) Apple MacBook Pro 15" (2011) Apple MacBook Pro 15" (2012) Toshiba Tecra A11 source_min > source_max WARN_ON(%s) target_min > target_max panel->backlight.max == 0 bad panel fit mode: %d
set backlight PWM = %d
backlight already enabled
util pin already enabled
get backlight PWM = %d
panel->backlight.device intel_backlight no backlight present per VBT
!panel->backlight.setup disabled enabled pipe %c
%02X (%s) (%02X) SDVOC SDVOB %s: W: %02X %s
I2c transfer returned %d
I2c transfer returned %d/%d
i2c transfer returned %d
(??? %d) %02X %s: R: %s
%s: R: ... failed
[CONNECTOR:%d:%s]
SDVO response %d %d [%x]
initialising DVI device %d
No enhancement is supported
left_margin right_margin top_margin bottom_margin hpos vpos saturation contrast hue sharpness brightness flicker_filter flicker_filter_adaptive flicker_filter_2d tv_chroma_filter tv_luma_filter dot_crawl dot crawl: current %d
initialising TV type %d
mode initialising LVDS device %d
SDVO DDC proxy No SDVO device found on %s
failed to retrieve SDVO DTD
forcing bpc to 8 for SDVO
couldn't fill AVI infoframe
SDVO_CMD_RESET SDVO_CMD_GET_DEVICE_CAPS SDVO_CMD_GET_FIRMWARE_REV SDVO_CMD_GET_TRAINED_INPUTS SDVO_CMD_GET_ACTIVE_OUTPUTS SDVO_CMD_SET_ACTIVE_OUTPUTS SDVO_CMD_GET_IN_OUT_MAP SDVO_CMD_SET_IN_OUT_MAP SDVO_CMD_GET_HOT_PLUG_SUPPORT SDVO_CMD_SET_ACTIVE_HOT_PLUG SDVO_CMD_GET_ACTIVE_HOT_PLUG SDVO_CMD_SET_TARGET_INPUT SDVO_CMD_SET_TARGET_OUTPUT SDVO_CMD_GET_CLOCK_RATE_MULT SDVO_CMD_SET_CLOCK_RATE_MULT SDVO_CMD_GET_TV_FORMAT SDVO_CMD_SET_TV_FORMAT SDVO_CMD_GET_POWER_STATE SDVO_CMD_GET_MAX_HPOS SDVO_CMD_GET_HPOS SDVO_CMD_SET_HPOS SDVO_CMD_GET_MAX_VPOS SDVO_CMD_GET_VPOS SDVO_CMD_SET_VPOS SDVO_CMD_GET_MAX_SATURATION SDVO_CMD_GET_SATURATION SDVO_CMD_SET_SATURATION SDVO_CMD_GET_MAX_HUE SDVO_CMD_GET_HUE SDVO_CMD_SET_HUE SDVO_CMD_GET_MAX_CONTRAST SDVO_CMD_GET_CONTRAST SDVO_CMD_SET_CONTRAST SDVO_CMD_GET_MAX_BRIGHTNESS SDVO_CMD_GET_BRIGHTNESS SDVO_CMD_SET_BRIGHTNESS SDVO_CMD_GET_MAX_OVERSCAN_H SDVO_CMD_GET_OVERSCAN_H SDVO_CMD_SET_OVERSCAN_H SDVO_CMD_GET_MAX_OVERSCAN_V SDVO_CMD_GET_OVERSCAN_V SDVO_CMD_SET_OVERSCAN_V SDVO_CMD_GET_FLICKER_FILTER SDVO_CMD_SET_FLICKER_FILTER SDVO_CMD_GET_MAX_SHARPNESS SDVO_CMD_GET_SHARPNESS SDVO_CMD_SET_SHARPNESS SDVO_CMD_GET_DOT_CRAWL SDVO_CMD_SET_DOT_CRAWL SDVO_CMD_GET_TV_CHROMA_FILTER SDVO_CMD_SET_TV_CHROMA_FILTER SDVO_CMD_GET_TV_LUMA_FILTER SDVO_CMD_SET_TV_LUMA_FILTER SDVO_CMD_GET_SUPP_ENCODE SDVO_CMD_GET_ENCODE SDVO_CMD_SET_ENCODE SDVO_CMD_SET_PIXEL_REPLI SDVO_CMD_GET_PIXEL_REPLI SDVO_CMD_GET_COLORIMETRY_CAP SDVO_CMD_SET_COLORIMETRY SDVO_CMD_GET_COLORIMETRY SDVO_CMD_SET_AUDIO_STAT SDVO_CMD_GET_AUDIO_STAT SDVO_CMD_GET_HBUF_INDEX SDVO_CMD_SET_HBUF_INDEX SDVO_CMD_GET_HBUF_INFO SDVO_CMD_GET_HBUF_AV_SPLIT SDVO_CMD_SET_HBUF_AV_SPLIT SDVO_CMD_GET_HBUF_TXRATE SDVO_CMD_SET_HBUF_TXRATE SDVO_CMD_SET_HBUF_DATA SDVO_CMD_GET_HBUF_DATA Power on Success Not supported Invalid arg Pending Target not specified Scaling not supported NTSC_M NTSC_J NTSC_443 PAL_B PAL_D PAL_G PAL_H PAL_I PAL_M PAL_N PAL_NC PAL_60 SECAM_B SECAM_D SECAM_G SECAM_K SECAM_K1 SECAM_L SECAM_60 forcing bpc to 8 for TV
[CONNECTOR:%d:%s] force=%d
TV detected: %x, %x
Unrecognised TV connection
NTSC-M NTSC-443 NTSC-J PAL-M PAL-N PAL 480p 576p 720p@60Hz 720p@50Hz 1080i@50Hz 1080i@60Hz 640x480 800x600 1024x768 1280x1024 848x480 1280x720 1920x1080 VGT deballoon.
VGT balloon fail
Unknown parameter %d
copy_to_user failed
failed to idle hardware: %d
WARN_ON(%s) &dev_priv->backlight_lock &dev_priv->sb_lock &dev_priv->csr_lock &dev_priv->av_mutex has_fpga_dbg, has_ddi, has_llc, supports_tv, overlay_needs_physical, has_overlay, cursor_needs_physical, has_hotplug, has_pipe_cxsr, has_fbc, is_preliminary, is_skylake, is_haswell, is_valleyview, is_ivybridge, is_crestline, is_broadwater, is_pineview, is_g4x, need_gfx_hws, is_g33, is_i945gm, is_i915g, is_i85x, is_mobile, bridge device not found
failed to map registers
inteldrmfb i915 i915-dp i915-hangcheck i915 MCHBAR failed bus alloc: %d
slice total: %u
subslice total: %u
subslice per slice: %u
EU total: %u
EU per subslice: %u
n y has slice power gating: %s
has EU power gating: %s
failed to init modeset
<6>i915: switched on
<3>i915: switched off
I915_INIT I915_FLUSH I915_FLIP I915_BATCHBUFFER I915_IRQ_EMIT I915_IRQ_WAIT I915_GETPARAM I915_SETPARAM I915_ALLOC I915_FREE I915_INIT_HEAP I915_CMDBUFFER I915_DESTROY_HEAP I915_SET_VBLANK_PIPE I915_GET_VBLANK_PIPE I915_VBLANK_SWAP I915_HWS_ADDR I915_GEM_INIT I915_GEM_EXECBUFFER I915_GEM_PIN I915_GEM_UNPIN I915_GEM_BUSY I915_GEM_THROTTLE I915_GEM_ENTERVT I915_GEM_LEAVEVT I915_GEM_CREATE I915_GEM_PREAD I915_GEM_PWRITE I915_GEM_MMAP I915_GEM_SET_DOMAIN I915_GEM_SW_FINISH I915_GEM_SET_TILING I915_GEM_GET_TILING I915_GEM_GET_APERTURE I915_GEM_MMAP_GTT I915_GET_PIPE_FROM_CRTC_ID I915_GEM_MADVISE I915_OVERLAY_PUT_IMAGE I915_OVERLAY_ATTRS I915_GEM_EXECBUFFER2 I915_GET_SPRITE_COLORKEY I915_SET_SPRITE_COLORKEY I915_GEM_WAIT I915_GEM_CONTEXT_CREATE I915_GEM_CONTEXT_DESTROY I915_GEM_SET_CACHING I915_GEM_GET_CACHING I915_REG_READ I915_GET_RESET_STATS I915_GEM_USERPTR I915_GEM_CONTEXT_GETPARAM I915_GEM_CONTEXT_SETPARAM . . 1 . 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 . . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 . . . 1 1 . . . . . . . 1 1 1 1 1 1 1 1 1 1 1 1 1 . 1 1 . 0 / . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 / . . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / . 0 / 1 1 . . . . . . . . . . . . 1 . . . . . . . . . 1 . 1 1 1 1 1 1 1 . . . . . . . . . . . . . 1 1 . 1 1 1 1 1 1 1 . . . . . . . . . . 1 0 1 0 . . . . . . . . . . . . . . . . . . . . . . 1 1 0 \ @ PK P xP ` UV p ^ _ h N I F V 0 F @ P $ ` #A p CE ] [ ͇ - э e Ԕ 9 Q 0 ` @ c P ` @ p 5 ) ` 0 @ # P ` % p Y hr = ͛
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license=GPL and additional rights description=Intel Graphics author=Intel Corporation author=Tungsten Graphics, Inc. parm=guc_log_level:GuC firmware logging level (-1:disabled (default), 0-3:enabled) parmtype=guc_log_level:int parm=enable_guc_submission:Enable GuC submission (default:false) parmtype=enable_guc_submission:bool parm=edp_vswing:Ignore/Override vswing pre-emph table selection from VBT (0=use value from vbt [default], 1=low power swing(200mV),2=default swing(400mV)) parmtype=edp_vswing:int parm=nuclear_pageflip:Force atomic modeset functionality; asynchronous mode is not yet supported. (default: false). parmtype=nuclear_pageflip:bool parm=verbose_state_checks:Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state conditions. parmtype=verbose_state_checks:bool parm=mmio_debug:Enable the MMIO debug code for the first N failures (default: off). This may negatively affect performance. parmtype=mmio_debug:int parm=use_mmio_flip:use MMIO flips (-1=never, 0=driver discretion [default], 1=always) parmtype=use_mmio_flip:int parm=enable_cmd_parser:Enable command parsing (1=enabled [default], 0=disabled) parmtype=enable_cmd_parser:int parm=disable_vtd_wa:Disable all VT-d workarounds (default: false) parmtype=disable_vtd_wa:bool parm=disable_display:Disable display (default: false) parmtype=disable_display:bool parm=invert_brightness:Invert backlight brightness (-1 force normal, 0 machine defaults, 1 force inversion), please report PCI device ID, subsystem vendor and subsystem device ID to dri-devel@lists.freedesktop.org, if your machine needs it. It will then be included in an upcoming module version. parmtype=invert_brightness:int parm=load_detect_test:Force-enable the VGA load detect code for testing (default:false). For developers only. parmtype=load_detect_test:bool parm=prefault_disable:Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only. parmtype=prefault_disable:bool parm=fastboot:Try to skip unnecessary mode sets at boot time (default: false) parmtype=fastboot:bool parm=enable_ips:Enable IPS (default: true) parmtype=enable_ips:int parm=disable_power_well:Disable display power wells when possible (-1=auto [default], 0=power wells always on, 1=power wells disabled when possible) parmtype=disable_power_well:int parm=preliminary_hw_support:Enable preliminary hardware support. parmtype=preliminary_hw_support:int parm=enable_psr:Enable PSR (default: false) parmtype=enable_psr:int parm=enable_execlists:Override execlists usage. (-1=auto [default], 0=disabled, 1=enabled) parmtype=enable_execlists:int parm=enable_ppgtt:Override PPGTT usage. (-1=auto [default], 0=disabled, 1=aliasing, 2=full) parmtype=enable_ppgtt:int parm=enable_hangcheck:Periodically check GPU activity for detecting hangs. WARNING: Disabling this can cause system wide hangs. (default: true) parmtype=enable_hangcheck:bool parm=reset:Attempt GPU resets (default: true) parmtype=reset:bool parm=vbt_sdvo_panel_type:Override/Ignore selection of SDVO panel mode in the VBT (-2=ignore, -1=auto [default], index in VBT BIOS table) parmtype=vbt_sdvo_panel_type:int parm=lvds_use_ssc:Use Spread Spectrum Clock with panels [LVDS/eDP] (default: auto from VBT) parmtype=lvds_use_ssc:int parm=lvds_channel_mode:Specify LVDS channel mode (0=probe BIOS [default], 1=single-channel, 2=dual-channel) parmtype=lvds_channel_mode:int parm=enable_fbc:Enable frame buffer compression for power savings (default: -1 (use per-chip default)) parmtype=enable_fbc:int parm=enable_rc6:Enable power-saving render C-state 6. Different stages can be selected via bitmask values (0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. default: -1 (use per-chip default) parmtype=enable_rc6:int parm=semaphores:Use semaphores for inter-ring sync (default: -1 (use per-chip defaults)) parmtype=semaphores:int parm=panel_ignore_lid:Override lid status (0=autodetect, 1=autodetect disabled [default], -1=force lid closed, -2=force lid open) parmtype=panel_ignore_lid:int parm=modeset:Use kernel modesetting [KMS] (0=disable, 1=on, -1=force vga console preference [default]) parmtype=modeset:int firmware=i915/bxt_dmc_ver1.bin firmware=i915/skl_dmc_ver1.bin firmware=i915/skl_guc_ver4.bin srcversion=F6C55014CE3615B8C193642 alias=pci:v00008086d00005A84sv*sd*bc03sc*i* alias=pci:v00008086d00001A84sv*sd*bc03sc*i* alias=pci:v00008086d00000A84sv*sd*bc03sc*i* alias=pci:v00008086d0000193Asv*sd*bc03sc*i* alias=pci:v00008086d0000193Dsv*sd*bc03sc*i* alias=pci:v00008086d0000193Bsv*sd*bc03sc*i* alias=pci:v00008086d00001932sv*sd*bc03sc*i* alias=pci:v00008086d0000192Asv*sd*bc03sc*i* alias=pci:v00008086d0000192Bsv*sd*bc03sc*i* alias=pci:v00008086d00001926sv*sd*bc03sc*i* alias=pci:v00008086d0000191Dsv*sd*bc03sc*i* alias=pci:v00008086d0000191Asv*sd*bc03sc*i* alias=pci:v00008086d0000191Bsv*sd*bc03sc*i* alias=pci:v00008086d00001912sv*sd*bc03sc*i* alias=pci:v00008086d0000191Esv*sd*bc03sc*i* alias=pci:v00008086d00001921sv*sd*bc03sc*i* alias=pci:v00008086d00001916sv*sd*bc03sc*i* alias=pci:v00008086d0000190Asv*sd*bc03sc*i* alias=pci:v00008086d0000190Bsv*sd*bc03sc*i* alias=pci:v00008086d00001902sv*sd*bc03sc*i* alias=pci:v00008086d0000190Esv*sd*bc03sc*i* alias=pci:v00008086d00001906sv*sd*bc03sc*i* alias=pci:v00008086d000022B3sv*sd*bc03sc*i* alias=pci:v00008086d000022B2sv*sd*bc03sc*i* alias=pci:v00008086d000022B1sv*sd*bc03sc*i* alias=pci:v00008086d000022B0sv*sd*bc03sc*i* alias=pci:v00008086d0000162Dsv*sd*bc03sc*i* alias=pci:v00008086d0000162Asv*sd*bc03sc*i* alias=pci:v00008086d0000162Esv*sd*bc03sc*i* alias=pci:v00008086d0000162Bsv*sd*bc03sc*i* alias=pci:v00008086d00001626sv*sd*bc03sc*i* alias=pci:v00008086d00001622sv*sd*bc03sc*i* alias=pci:v00008086d0000161Dsv*sd*bc03sc*i* alias=pci:v00008086d0000161Asv*sd*bc03sc*i* alias=pci:v00008086d0000160Dsv*sd*bc03sc*i* alias=pci:v00008086d0000160Asv*sd*bc03sc*i* alias=pci:v00008086d0000161Esv*sd*bc03sc*i* alias=pci:v00008086d0000161Bsv*sd*bc03sc*i* alias=pci:v00008086d00001616sv*sd*bc03sc*i* alias=pci:v00008086d00001612sv*sd*bc03sc*i* alias=pci:v00008086d0000160Esv*sd*bc03sc*i* alias=pci:v00008086d0000160Bsv*sd*bc03sc*i* alias=pci:v00008086d00001606sv*sd*bc03sc*i* alias=pci:v00008086d00001602sv*sd*bc03sc*i* alias=pci:v00008086d00000155sv*sd*bc03sc*i* alias=pci:v00008086d00000157sv*sd*bc03sc*i* alias=pci:v00008086d00000F33sv*sd*bc03sc*i* alias=pci:v00008086d00000F32sv*sd*bc03sc*i* alias=pci:v00008086d00000F31sv*sd*bc03sc*i* alias=pci:v00008086d00000F30sv*sd*bc03sc*i* alias=pci:v00008086d00000D26sv*sd*bc03sc*i* alias=pci:v00008086d00000D16sv*sd*bc03sc*i* alias=pci:v00008086d00000D06sv*sd*bc03sc*i* alias=pci:v00008086d00000A2Esv*sd*bc03sc*i* alias=pci:v00008086d00000A1Esv*sd*bc03sc*i* alias=pci:v00008086d00000A0Esv*sd*bc03sc*i* alias=pci:v00008086d00000A26sv*sd*bc03sc*i* alias=pci:v00008086d00000A16sv*sd*bc03sc*i* alias=pci:v00008086d00000A06sv*sd*bc03sc*i* alias=pci:v00008086d00000C26sv*sd*bc03sc*i* alias=pci:v00008086d00000C16sv*sd*bc03sc*i* alias=pci:v00008086d00000C06sv*sd*bc03sc*i* alias=pci:v00008086d00000426sv*sd*bc03sc*i* alias=pci:v00008086d00000416sv*sd*bc03sc*i* alias=pci:v00008086d00000406sv*sd*bc03sc*i* alias=pci:v00008086d00000D2Esv*sd*bc03sc*i* alias=pci:v00008086d00000D1Esv*sd*bc03sc*i* alias=pci:v00008086d00000D0Esv*sd*bc03sc*i* alias=pci:v00008086d00000D2Bsv*sd*bc03sc*i* alias=pci:v00008086d00000D1Bsv*sd*bc03sc*i* alias=pci:v00008086d00000D0Bsv*sd*bc03sc*i* alias=pci:v00008086d00000D2Asv*sd*bc03sc*i* alias=pci:v00008086d00000D1Asv*sd*bc03sc*i* alias=pci:v00008086d00000D0Asv*sd*bc03sc*i* alias=pci:v00008086d00000D22sv*sd*bc03sc*i* alias=pci:v00008086d00000D12sv*sd*bc03sc*i* alias=pci:v00008086d00000D02sv*sd*bc03sc*i* alias=pci:v00008086d00000A2Bsv*sd*bc03sc*i* alias=pci:v00008086d00000A1Bsv*sd*bc03sc*i* alias=pci:v00008086d00000A0Bsv*sd*bc03sc*i* alias=pci:v00008086d00000A2Asv*sd*bc03sc*i* alias=pci:v00008086d00000A1Asv*sd*bc03sc*i* alias=pci:v00008086d00000A0Asv*sd*bc03sc*i* alias=pci:v00008086d00000A22sv*sd*bc03sc*i* alias=pci:v00008086d00000A12sv*sd*bc03sc*i* alias=pci:v00008086d00000A02sv*sd*bc03sc*i* alias=pci:v00008086d00000C2Esv*sd*bc03sc*i* alias=pci:v00008086d00000C1Esv*sd*bc03sc*i* alias=pci:v00008086d00000C0Esv*sd*bc03sc*i* alias=pci:v00008086d00000C2Bsv*sd*bc03sc*i* alias=pci:v00008086d00000C1Bsv*sd*bc03sc*i* alias=pci:v00008086d00000C0Bsv*sd*bc03sc*i* alias=pci:v00008086d00000C2Asv*sd*bc03sc*i* alias=pci:v00008086d00000C1Asv*sd*bc03sc*i* alias=pci:v00008086d00000C0Asv*sd*bc03sc*i* alias=pci:v00008086d00000C22sv*sd*bc03sc*i* alias=pci:v00008086d00000C12sv*sd*bc03sc*i* alias=pci:v00008086d00000C02sv*sd*bc03sc*i* alias=pci:v00008086d0000042Esv*sd*bc03sc*i* alias=pci:v00008086d0000041Esv*sd*bc03sc*i* alias=pci:v00008086d0000040Esv*sd*bc03sc*i* alias=pci:v00008086d0000042Bsv*sd*bc03sc*i* alias=pci:v00008086d0000041Bsv*sd*bc03sc*i* alias=pci:v00008086d0000040Bsv*sd*bc03sc*i* alias=pci:v00008086d0000042Asv*sd*bc03sc*i* alias=pci:v00008086d0000041Asv*sd*bc03sc*i* alias=pci:v00008086d0000040Asv*sd*bc03sc*i* alias=pci:v00008086d00000422sv*sd*bc03sc*i* alias=pci:v00008086d00000412sv*sd*bc03sc*i* alias=pci:v00008086d00000402sv*sd*bc03sc*i* alias=pci:v00008086d0000016Asv*sd*bc03sc*i* alias=pci:v00008086d0000015Asv*sd*bc03sc*i* alias=pci:v00008086d00000162sv*sd*bc03sc*i* alias=pci:v00008086d00000152sv*sd*bc03sc*i* alias=pci:v00008086d00000166sv*sd*bc03sc*i* alias=pci:v00008086d00000156sv*sd*bc03sc*i* alias=pci:v00008086d0000016Asv0000152Dsd00008990bc03sc*i* alias=pci:v00008086d00000126sv*sd*bc03sc*i* alias=pci:v00008086d00000116sv*sd*bc03sc*i* alias=pci:v00008086d00000106sv*sd*bc03sc*i* alias=pci:v00008086d0000010Asv*sd*bc03sc*i* alias=pci:v00008086d00000122sv*sd*bc03sc*i* alias=pci:v00008086d00000112sv*sd*bc03sc*i* alias=pci:v00008086d00000102sv*sd*bc03sc*i* alias=pci:v00008086d00000046sv*sd*bc03sc*i* alias=pci:v00008086d00000042sv*sd*bc03sc*i* alias=pci:v00008086d0000A011sv*sd*bc03sc*i* alias=pci:v00008086d0000A001sv*sd*bc03sc*i* alias=pci:v00008086d00002E92sv*sd*bc03sc*i* alias=pci:v00008086d00002E42sv*sd*bc03sc*i* alias=pci:v00008086d00002E32sv*sd*bc03sc*i* alias=pci:v00008086d00002E22sv*sd*bc03sc*i* alias=pci:v00008086d00002E12sv*sd*bc03sc*i* alias=pci:v00008086d00002E02sv*sd*bc03sc*i* alias=pci:v00008086d00002A42sv*sd*bc03sc*i* alias=pci:v00008086d00002A12sv*sd*bc03sc*i* alias=pci:v00008086d00002A02sv*sd*bc03sc*i* alias=pci:v00008086d000029D2sv*sd*bc03sc*i* alias=pci:v00008086d000029C2sv*sd*bc03sc*i* alias=pci:v00008086d000029B2sv*sd*bc03sc*i* alias=pci:v00008086d000029A2sv*sd*bc03sc*i* alias=pci:v00008086d00002992sv*sd*bc03sc*i* alias=pci:v00008086d00002982sv*sd*bc03sc*i* alias=pci:v00008086d00002972sv*sd*bc03sc*i* alias=pci:v00008086d000027AEsv*sd*bc03sc*i* alias=pci:v00008086d000027A2sv*sd*bc03sc*i* alias=pci:v00008086d00002772sv*sd*bc03sc*i* alias=pci:v00008086d00002592sv*sd*bc03sc*i* alias=pci:v00008086d0000258Asv*sd*bc03sc*i* alias=pci:v00008086d00002582sv*sd*bc03sc*i* alias=pci:v00008086d00002572sv*sd*bc03sc*i* alias=pci:v00008086d0000358Esv*sd*bc03sc*i* alias=pci:v00008086d00003582sv*sd*bc03sc*i* alias=pci:v00008086d00002562sv*sd*bc03sc*i* alias=pci:v00008086d00003577sv*sd*bc03sc*i* depends=drm_kms_helper,drm,i2c-core,video,i2c-algo-bit vermagic=2.6.32-696.20.1.el6.x86_64 SMP mod_unload modversions @ @ j @ @ @ , ( @ N 0 @ 8 @ > @ @ r H @ %
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drm_get_connector_status_name z= up_read
n drm_dp_dpcd_write *\= drm_calc_timestamping_constants ~^Z simple_read_from_buffer ժ drm_get_edid T, drm_atomic_helper_update_plane z6~ sysfs_remove_bin_file .п drm_crtc_index drm_rect_calc_vscale
~/ trace_profile_buf_nmi 6 drm_fb_helper_cfb_fillrect + ioremap_wc A1 drm_calc_vbltimestamp_from_scanoutpos
N drm_framebuffer_reference qR| single_open 6a drm_fb_helper_initial_config nuz kvfree i param_get_int idr2_for_each drm_connector_index `)D drm_hdmi_vendor_infoframe_from_display_mode St drm_edid_to_eld Xi iomem_resource (% strlen Y drm_wait_one_vblank * intel_gmch_probe z\ ida2_init 8 schedule_timeout_uninterruptible 5Q( acpi_evaluate_integer ӓJ release_resource
2 pci_unmap_rom ! drm_gem_dmabuf_release _ӯ drm_mode_config_cleanup I component_add iin drm_modeset_drop_locks _
vga_get 'C memset_io }" devm_kzalloc q U. drm_mode_config_reset '| autoremove_wake_function =v drm_pci_exit sg_nents J drm_atomic_state_clear eW cpufreq_cpu_get kp __copy_user_nocache 8q sg_copy_from_buffer V interval_tree_insert x single_release +1 drm_mode_destroy drm_match_cea_mode ˑ malloc_sizes oF seq_puts boot_cpu_data RB, mipi_dsi_dcs_write_buffer # dma_buf_detach pci_disable_device < arch_phys_wc_add w drm_property_create_range J drm_atomic_helper_swap_state h drm_dp_mst_topology_mgr_resume ? i2c_transfer 'j> drm_atomic_get_plane_state @ drm_mm_scan_add_block ؐ~ perf_swevent_put_recursion_context x intel_enable_gtt 4c vga_switcheroo_process_delayed_switch Hr drm_rect_calc_vscale_relaxed 3E usecs_to_jiffies backlight_device_register qooR drm_rect_calc_hscale_relaxed s8 _spin_lock v schedule_work drm_modeset_backoff ѣ find_next_bit A acpi_bus_get_device xPA drm_dp_mst_topology_mgr_set_mst schedule_timeout_killable ݫ3 drm_helper_probe_single_connector_modes o?w seq_printf &l drm_crtc_vblank_off p cancel_work_sync /u perf_tp_event_regs ^ sysfs_create_files M __mmu_notifier_register | ktime_get yL pci_get_class v~ queue_work QL seq_write __sg_page_iter_start kmemdup &x drm_dp_calc_pbn_mode ? sg_next ǎ acpi_evaluate_object list_sort sg_pcopy_from_buffer U( drm_gem_free_mmap_offset bY __get_user_pages_fast iW drm_vblank_cleanup >\ pm_qos_add_requirement __const_udelay N perf_swevent_get_recursion_context # hdmi_infoframe_pack }i try_acquire_console_sem &j init_timer_key Tt2 ring_buffer_event_data _Y drm_kms_helper_hotplug_event ) drm_mm_insert_node_in_range_generic 0 cancel_delayed_work_sync u mutex_unlock 9 bitmap_set @k hweight32 I drm_panel_init b& drm_dp_mst_topology_mgr_destroy ` drm_vblank_init _a1 pci_bus_write_config_word %K param_set_int D drm_encoder_init b_|b drm_dp_mst_hpd_irq drm_modeset_acquire_fini /z drm_pci_free 5U drm_object_property_set_value debugfs_create_file ^M pci_bus_alloc_resource D tsc_khz *q _spin_lock_irqsave ~ filter_current_check_discard shmem_truncate_range `] __drm_atomic_helper_crtc_destroy_state . seq_read i trace_nowake_buffer_unlock_commit vl'F drm_av_sync_delay z drm_detect_monitor_audio ;& acpi_video_register drm_universal_plane_init \9 drm_dp_mst_allocate_vcpi + drm_mm_init_scan IBC set_page_dirty - drm_pci_set_busid 8( vga_put 4 drm_dp_channel_eq_ok h} jiffies C __list_add O+~ drm_connector_cleanup i2c_add_adapter R
mutex_trylock
__mmdrop q= pci_mem_start Z% strcmp N down_read __drm_atomic_helper_plane_duplicate_state __drm_atomic_helper_crtc_duplicate_state __init_waitqueue_head drm_fb_helper_pan_display C)wx drm_atomic_helper_update_legacy_modeset_state jH) per_cpu__cpu_number j drm_rect_debug_print 謁 drm_atomic_helper_set_config drm_handle_vblank -. vga_switcheroo_unregister_client cU pci_set_master . hweight16 + __bitmap_or nd drm_dp_mst_deallocate_vcpi 铰 drm_dp_check_act_status p?l round_jiffies_up_relative pP pgprot_writecombine <] drm_fb_helper_set_suspend Sl pci_get_bus_and_slot del_timer_sync tg trace_define_field mT drm_mm_init ^+ acpi_is_video_device ` dmi_check_system memset :7t' ida2_simple_get K drm_mode_connector_attach_encoder JH drm_irq_install j drm_atomic_state_alloc ɵ drm_fb_helper_cfb_copyarea jA remove_conflicting_framebuffers ٖ drm_mode_connector_set_path_property J q drm_dp_link_rate_to_bw_code I/ drm_mode_copy pci_set_dma_mask D drm_noop V default_llseek drm_atomic_commit 96H acpi_lid_open >t drm_plane_index 8 _ctype t pci_iounmap $ hweight8 X dev_err b drm_clflush_sg
B drm_mode_set_name p7 jiffies_to_msecs 5QM mutex_lock_interruptible gi drm_crtc_vblank_put 9K __mutex_init ]V! drm_helper_mode_fill_fb_struct RR __memcpy_toio cs printk CcY drm_object_attach_property B"B sscanf c drm_atomic_helper_prepare_planes _spin_lock_irq N? drm_mode_duplicate 0< drm_mode_create_tv_properties drm_has_preferred_mode drm_crtc_init_with_planes vG drm_put_dev 0n drm_rect_rotate_inv 0 unregister_acpi_notifier L async_synchronize_full O& mmu_notifier_unregister - drm_gem_handle_create 2If drm_dp_mst_reset_vcpi_slots x I drm_mm_reserve_node " drm_gem_dumb_destroy ]> vmap uX acpi_lid_notifier_unregister 2: intel_gtt_chipset_flush l__ pci_map_rom G drm_dp_link_train_clock_recovery_delay a drm_mode_create_rotation_property Xx drm_dp_get_adjust_request_voltage a- param_set_bool ~:/ dma_buf_put $^# drm_fb_helper_fill_var 3 shmem_read_mapping_page_gfp Yqo drm_plane_from_index < drm_atomic_state_init
nǡ _cond_resched f copy_to_user ~ strncpy 9 mcount 6* seq_putc TӞ drm_panel_attach debugfs_remove `y intel_iommu_gfx_mapped
)s kmem_cache_free ও io_schedule tQ^ swiotlb_nr_tbl ld drm_send_vblank_event R0 warn_slowpath_null ) pci_bus_write_config_dword mutex_lock m per_cpu__kernel_stack ڐ! drm_select_eld vga_client_register drm_probe_ddc l destroy_workqueue drm_dp_mst_topology_mgr_suspend 'y __sg_page_iter_next [D! list_del YD drm_gem_object_release b drm_framebuffer_unreference drm_modeset_legacy_acquire_ctx sysfs_merge_group m9 drm_read `` interval_tree_iter_next $ noop_llseek yK _spin_unlock_irqrestore c EE mod_timer XL trace_define_common_fields b^ drm_add_edid_modes ̶o drm_property_add_enum t pid_task E u
drm_dp_aux_unregister hLf simple_attr_release P=7 kstrtoint {*\ sysfs_remove_link __create_workqueue_key @_ drm_fb_helper_release_fbi H dma_buf_unmap_attachment )& trace_current_buffer_lock_reserve _l drm_atomic_set_fb_for_plane y3 request_firmware_nowait ϭ mipi_dsi_generic_write xQ up_write drm_fb_helper_add_one_connector CUE down_write +U sysfs_unmerge_group 2 drm_debugfs_create_files release_pages z drm_err zE drm_connector_init drm_kms_helper_poll_enable ! flush_workqueue 0ũ unregister_oom_notifier XYJ idr2_find_slowpath Ƀ~ async_schedule N% drm_fb_helper_prepare hG drm_gem_vm_open m6HL drm_mode_connector_update_edid_property < kobject_uevent_env ˄ __symbol_get 3 drm_modeset_unlock _ drm_dp_mst_dump_topology < drm_gem_vm_close M5 drm_modeset_lock i mark_page_accessed u# synchronize_irq {7Ez acpi_video_unregister trace_profile_buf BVd drm_debug k~ do_mmap_pgoff 9 unregister_reboot_notifier Hk register_ftrace_event + acpi_get_handle zk drm_crtc_get_hv_timing VW per_cpu__this_cpu_off ? drm_gem_object_free M idr2_destroy ` I sg_alloc_table l work_busy rt drm_atomic_get_crtc_state m= sysfs_create_link R pm_qos_update_requirement 1q drm_gem_prime_fd_to_handle 8 find_vma } capable
vf drm_atomic_helper_plane_set_property - i2c_del_adapter drm_framebuffer_remove uE drm_mode_set_crtcinfo u drm_plane_cleanup
{* drm_ioctl g drm_dp_find_vcpi_slots f drm_property_create_enum \ kmem_cache_alloc NOvx pv_irq_ops ~ drm_mode_create p drm_gem_mmap Z __free_pages K drm_mode_hsync g^ intel_gtt_get T drm_atomic_helper_wait_for_vblanks drm_atomic_set_crtc_for_plane 5B ioremap_nocache fI6 dma_buf_map_attachment : drm_clflush_pages G usleep_range S pci_bus_read_config_word ր5 drm_atomic_helper_connector_destroy_state m.\ drm_mode_create_scaling_mode_property q register_reboot_notifier DT/ dma_buf_export fm pci_bus_read_config_dword register_acpi_notifier Z@ drm_framebuffer_unregister_private 2' tracing_generic_entry_update drm_crtc_vblank_reset C drm_kms_helper_poll_enable_locked __stack_chk_fail ;)n get_user_pages @ schedule_delayed_work 7 ida2_simple_remove ) drm_fb_helper_check_var drm_gem_private_object_init ; msecs_to_jiffies 3 drm_mode_create_aspect_ratio_property $ drm_dp_get_adjust_request_pre_emphasis [r drm_fb_helper_blank Q schedule ?, schedule_timeout er
drm_clflush_virt_range x# drm_dp_mst_get_edid pd vga_switcheroo_client_fb_set NB drm_irq_uninstall fV_ per_cpu__ftrace_event_seq @: drm_get_pci_dev sJ unregister_shrinker2 j flush_delayed_work ] register_oom_notifier Ḓ ida2_destroy __devm_request_region intel_gtt_insert_sg_entries ڭS drm_rect_rotate \OC release_console_sem c/ acpi_get_name V{ acpi_lid_notifier_register 2R drm_mode_debug_printmodeline r acpi_target_system_state drm_modeset_unlock_crtc set_pages_wb Ht acquire_console_sem hd' pv_cpu_ops Q2 drm_dp_link_train_channel_eq_delay G drm_gem_object_lookup ri drm_crtc_vblank_get $b drm_pci_alloc ̚Z drm_fb_helper_hotplug_event s$ jiffies_to_usecs n drm_dp_mst_topology_mgr_init 8|l& wake_up_process w\ drm_mm_init_scan_with_range _ device_create_bin_file ; drm_format_plane_cpp x[ drm_panel_remove fÚ interval_tree_iter_first f __memcpy_fromio D kmem_cache_alloc_trace ́ drm_fb_helper_alloc_fbi
w drm_detect_hdmi_monitor cpufreq_cpu_put z2 __per_cpu_offset 9M drm_atomic_helper_connector_dpms 6D dma_buf_attach drm_gem_prime_handle_to_fd 9 kmem_cache_create e5 vsnprintf {Ā drm_modeset_acquire_init T.d __wake_up jV drm_connector_unregister ~ drm_gem_object_init YHg drm_encoder_cleanup pci_set_power_state sw sysfs_remove_files O intel_gmch_remove Ƈ. do_gettimeofday yv(r drm_gem_create_mmap_offset '}M pci_bus_write_config_byte x drm_get_format_name :j warn_slowpath_fmt cC mipi_dsi_attach N drm_crtc_cleanup x drm_edid_duplicate \ seq_lseek FgP getrawmonotonic xL drm_atomic_helper_commit_planes_on_crtc v& __vmalloc 1: kref_init | drm_atomic_helper_crtc_destroy_state l i2c_bit_algo d'm __bitmap_empty +fo drm_plane_helper_check_update LA drm_mode_config_init z kfree vunmap ^ drm_helper_hpd_irq_event /o kstrtouint drm_hdmi_avi_infoframe_from_display_mode !o 1 unmap_mapping_range ;5 component_del dl# memcpy x flush_scheduled_work /3 prepare_to_wait -$ pci_disable_msi Qr skip_spaces :~ nsecs_to_jiffies64 dma_supported MO mod_delayed_work Bw drm_get_subpixel_order_name kref_get S9 iounmap U sysfs_create_bin_file c2Q vga_switcheroo_register_client compat_alloc_user_space 5 i drm_rect_clip_scaled 9 drm_panel_detach $0 invalidate_mapping_pages cr ioremap_cache :~
mipi_dsi_create_packet B5X __put_task_struct - drm_fb_helper_cfb_imageblit ܺU __copy_from_user_inatomic 'X drm_atomic_helper_cleanup_planes r put_page P@ scnprintf drm_atomic_state_default_clear U set_pages_uc xe request_firmware aR idr2_alloc (J drm_fb_helper_remove_one_connector d, sg_alloc_table_from_pages %F drm_debugfs_remove_files J` drm_fb_helper_fini ~R find_first_bit ! drm_modeset_lock_all ! drm_mm_takedown "&˜ finish_wait O get_pid_task ڰ\ drm_crtc_vblank_count qѻL __bitmap_weight WP- drm_rect_calc_hscale param_get_bool .Zd sg_free_table w drm_atomic_helper_disable_plane L pci_dev_put 3NI vm_get_page_prot ֝n __symbol_put o`u bad_dma_address zZ drm_atomic_add_affected_connectors (6 drm_fb_helper_restore_fbdev_mode_unlocked d drm_mode_probed_add L̯ drm_dp_update_payload_part2 w copy_user_generic ۞ snprintf kzj pci_enable_msi_block G hdmi_spd_infoframe_init q_ drm_modeset_unlock_all +G __pm_runtime_get LD- trace_seq_printf wP arch_phys_wc_del memmove m . drm_atomic_add_affected_planes Y÷ drm_fb_helper_setcmap 4t pci_iomap H drm_pci_init E! drm_property_create y drm_framebuffer_init ` drm_ut_debug_printk dF drm_mm_remove_node 0 pm_qos_remove_requirement / drm_kms_helper_poll_init - pcibios_align_resource y!lC iowrite32 T6NK drm_panel_add F drm_dp_dpcd_read * pci_enable_device % pci_set_consistent_dma_mask O5 drm_dp_mst_detect_port 0c backlight_device_unregister drm_dp_aux_register
drm_fb_helper_fill_fix drm_pick_cmdline_mode i idr2_init i; drm_connector_register d mod_timer_pinned : drm_mode_legacy_fb_format 3 copy_from_user <
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/ A \ S i915_drv.c i915_exit driver i915_pci_driver vlv_check_no_gt_access bxt_resume_prepare vlv_allow_gt_wake vlv_resume_prepare intel_runtime_resume __warned.53123 __func__.53140 i915_drm_suspend i915_drm_resume_early i915_drm_resume i915_pm_resume i915_pci_remove i915_pci_probe i915_init __func__.53456 __func__.51611 __func__.51503 intel_suspend_complete __func__.52778 intel_runtime_suspend __warned.52949 __warned.52954 __func__.52971 i915_drm_suspend_late i915_pm_poweroff i915_pm_suspend __warned.52212 __mod_license1778 __mod_description1777 __mod_author1775 __mod_author1774 i915_gem_vm_ops i915_driver_fops pciidlist i915_pm_ops intel_i830_info intel_845g_info intel_i85x_info intel_i865g_info intel_i915g_info intel_i915gm_info intel_i945g_info intel_i945gm_info intel_i965g_info intel_g33_info intel_i965gm_info intel_gm45_info intel_g45_info intel_pineview_info intel_ironlake_d_info intel_ironlake_m_info intel_sandybridge_d_info intel_sandybridge_m_info intel_ivybridge_q_info intel_ivybridge_m_info intel_ivybridge_d_info intel_haswell_d_info intel_haswell_m_info intel_valleyview_m_info intel_valleyview_d_info intel_broadwell_m_info intel_broadwell_d_info intel_broadwell_gt3m_info intel_broadwell_gt3d_info intel_cherryview_info intel_skylake_info intel_skylake_gt3_info intel_broxton_info i915_irq.c i8xx_get_vblank_counter i915_get_vblank_counter g4x_get_vblank_counter bxt_port_hotplug_long_detect spt_port_hotplug2_long_detect spt_port_hotplug_long_detect ilk_port_hotplug_long_detect pch_port_hotplug_long_detect i9xx_port_hotplug_long_detect ibx_irq_reset gen5_gt_irq_reset ironlake_irq_reset gen8_gt_irq_reset ironlake_irq_uninstall i8xx_irq_preinstall i8xx_irq_uninstall gen6_pm_rps_work ivybridge_parity_work i915_hangcheck_elapsed i915_get_vblank_timestamp i915_get_crtc_scanoutpos valleyview_irq_handler valleyview_irq_preinstall valleyview_irq_postinstall valleyview_irq_uninstall valleyview_enable_vblank valleyview_disable_vblank i915_hpd_irq_setup gen8_irq_handler gen8_irq_reset gen8_irq_postinstall gen8_irq_uninstall gen8_enable_vblank gen8_disable_vblank spt_hpd_irq_setup ilk_hpd_irq_setup i965_irq_preinstall i965_irq_postinstall i965_irq_uninstall i965_irq_handler i915_enable_vblank i915_disable_vblank ironlake_irq_handler ironlake_irq_postinstall ironlake_enable_vblank ironlake_disable_vblank cherryview_irq_handler cherryview_irq_preinstall cherryview_irq_postinstall cherryview_irq_uninstall bxt_hpd_irq_setup i8xx_irq_postinstall i8xx_irq_handler i915_irq_preinstall i915_irq_postinstall i915_irq_uninstall i915_irq_handler dp_aux_irq_handler gmbus_irq_handler intel_get_hpd_pins __func__.52856 i9xx_hpd_irq_handler hpd_status_i915 hpd_status_g4x ilk_hpd_irq_handler ibx_hpd_irq_handler notify_ring i915_error_wake_up i915_handle_vblank display_pipe_crc_irq_handler __func__.52911 i9xx_pipe_crc_irq_handler __func__.56594 __func__.56293 __func__.56023 valleyview_pipestat_irq_handler CSWTCH.1203 hsw_pipe_crc_irq_handler ibx_irq_pre_postinstall gen5_assert_iir_is_zero gen5_gt_irq_postinstall ibx_irq_postinstall gen8_gt_irq_postinstall bdw_update_port_irq hpd_bxt ilk_update_display_irq hpd_mask_i915 vlv_get_pipestat_enable_mask __warned.51636 __warned.51641 __warned.51575 valleyview_display_irqs_uninstall __warned.51509 i915_enable_asle_pipestat valleyview_display_irqs_install hpd_bdw hpd_cpt hpd_ivb hpd_ilk hpd_ibx hpd_spt snb_update_pm_irq ilk_update_gt_irq snb_gt_irq_handler __func__.52643 gen6_rps_irq_handler __func__.53062 cpt_irq_handler __func__.53525 __func__.53363 gen8_gt_irq_handler __func__.53953 __intel_get_crtc_scanline __func__.51927 __func__.52092 semaphore_passed __warned.52410 __func__.52424 vlv_c0_read i915_reset_and_wakeup __func__.54229 vlv_display_irq_reset vlv_display_irq_uninstall vlv_display_irq_postinstall .LC7 i915_params.c __mod_guc_log_level198 __mod_guc_log_leveltype196 __param_guc_log_level __param_str_guc_log_level __mod_enable_guc_submission194 __mod_enable_guc_submissiontype193 __param_enable_guc_submission __param_str_enable_guc_submission __mod_edp_vswing191 __mod_edp_vswingtype187 __param_edp_vswing __param_str_edp_vswing __mod_nuclear_pageflip184 __mod_nuclear_pagefliptype182 __param_nuclear_pageflip __param_str_nuclear_pageflip __mod_verbose_state_checks180 __mod_verbose_state_checkstype178 __param_verbose_state_checks __param_str_verbose_state_checks __mod_mmio_debug176 __mod_mmio_debugtype173 __param_mmio_debug __param_str_mmio_debug __mod_use_mmio_flip171 __mod_use_mmio_fliptype169 __param_use_mmio_flip __param_str_use_mmio_flip __mod_enable_cmd_parser167 __mod_enable_cmd_parsertype165 __param_enable_cmd_parser __param_str_enable_cmd_parser __mod_disable_vtd_wa163 __mod_disable_vtd_watype162 __param_disable_vtd_wa __param_str_disable_vtd_wa __mod_disable_display160 __mod_disable_displaytype159 __param_disable_display __param_str_disable_display __mod_invert_brightness157 __mod_invert_brightnesstype151 __param_invert_brightness __param_str_invert_brightness __mod_load_detect_test149 __mod_load_detect_testtype146 __param_load_detect_test __param_str_load_detect_test __mod_prefault_disable144 __mod_prefault_disabletype141 __param_prefault_disable __param_str_prefault_disable __mod_fastboot139 __mod_fastboottype137 __param_fastboot __param_str_fastboot __mod_enable_ips135 __mod_enable_ipstype134 __param_enable_ips __param_str_enable_ips __mod_disable_power_well132 __mod_disable_power_welltype129 __param_disable_power_well __param_str_disable_power_well __mod_preliminary_hw_support127 __mod_preliminary_hw_supporttype125 __param_preliminary_hw_support __param_str_preliminary_hw_support __mod_enable_psr123 __mod_enable_psrtype122 __param_enable_psr __param_str_enable_psr __mod_enable_execlists120 __mod_enable_execliststype117 __param_enable_execlists __param_str_enable_execlists __mod_enable_ppgtt115 __mod_enable_ppgtttype112 __param_enable_ppgtt __param_str_enable_ppgtt __mod_enable_hangcheck110 __mod_enable_hangchecktype106 __param_enable_hangcheck __param_str_enable_hangcheck __mod_reset104 __mod_resettype103 __param_reset __param_str_reset __mod_vbt_sdvo_panel_type101 __mod_vbt_sdvo_panel_typetype98 __param_vbt_sdvo_panel_type __param_str_vbt_sdvo_panel_type __mod_lvds_use_ssc96 __mod_lvds_use_ssctype93 __param_lvds_use_ssc __param_str_lvds_use_ssc __mod_lvds_channel_mode91 __mod_lvds_channel_modetype88 __param_lvds_channel_mode __param_str_lvds_channel_mode __mod_enable_fbc86 __mod_enable_fbctype83 __param_enable_fbc __param_str_enable_fbc __mod_enable_rc681 __mod_enable_rc6type75 __param_enable_rc6 __param_str_enable_rc6 __mod_semaphores73 __mod_semaphorestype70 __param_semaphores __param_str_semaphores __mod_panel_ignore_lid68 __mod_panel_ignore_lidtype65 __param_panel_ignore_lid __param_str_panel_ignore_lid __mod_modeset63 __mod_modesettype60 __param_modeset __param_str_modeset i915_suspend.c i915_sysfs.c error_state_attr gen6_attrs dpf_attrs_1 dpf_attrs rc6_attr_group rc6p_attr_group vlv_attrs show_rc6_mask calc_residency show_rc6pp_ms show_rc6p_ms show_rc6_ms show_media_rc6_ms vlv_rpe_freq_mhz_show gt_rp_mhz_show dev_attr_gt_RP0_freq_mhz dev_attr_gt_RP1_freq_mhz dev_attr_gt_RPn_freq_mhz gt_min_freq_mhz_show gt_max_freq_mhz_show gt_cur_freq_mhz_show gt_min_freq_mhz_store gt_max_freq_mhz_store __func__.51496 gt_act_freq_mhz_show i915_l3_write i915_l3_read error_state_write __func__.51697 error_state_read media_rc6_attr_group dev_attr_gt_act_freq_mhz dev_attr_gt_cur_freq_mhz dev_attr_gt_max_freq_mhz dev_attr_gt_min_freq_mhz dev_attr_vlv_rpe_freq_mhz power_group_name rc6_attrs rc6p_attrs media_rc6_attrs dev_attr_rc6_enable dev_attr_rc6_residency_ms dev_attr_rc6p_residency_ms dev_attr_rc6pp_residency_ms dev_attr_media_rc6_residency_ms .LC3 intel_csr.c finish_csr_load __func__.51384 skl_stepping_info bxt_stepping_info __func__.51297 __warned.51464 __warned.51479 __warned.51474 __warned.51469 __mod_firmware48 __mod_firmware47 intel_pm.c bxt_init_clock_gating ilk_plane_wm_max ilk_compute_wm_maximums skl_plane_relative_data_rate skl_compute_wm_results skl_ddb_entry_write skl_pipe_wm_active_state wm0_pipe_reg.56564 gen6_set_rps_thresholds CSWTCH.1629 CSWTCH.1627 CSWTCH.1628 g4x_disable_trickle_feed ilk_init_lp_watermarks ironlake_init_clock_gating cpt_init_clock_gating gen7_setup_fixed_func_scheduler lpt_init_clock_gating broadwell_init_clock_gating haswell_init_clock_gating vlv_init_display_clock_gating valleyview_init_clock_gating cherryview_init_clock_gating g4x_init_clock_gating crestline_init_clock_gating broadwater_init_clock_gating gen3_init_clock_gating i85x_init_clock_gating i830_init_clock_gating __key.62133 intel_gen6_powersave_work ilk_wm_method1 ilk_wm_method2 ilk_compute_wm_level skl_compute_plane_wm intel_print_rc6_info __func__.57905 intel_get_cxsr_latency cxsr_latency_table __func__.51342 i830_get_fifo_size __func__.51735 i845_get_fifo_size __func__.51767 intel_calculate_wm __func__.51809 i9xx_get_fifo_size __func__.51703 vlv_pipe_set_fifo_size __func__.52798 gen6_check_mch_setup __func__.60491 ivybridge_init_clock_gating gen6_init_clock_gating ilk_validate_wm_level __func__.53955 skl_wm_flush_pipe __func__.56119 __func__.57049 vlv_get_fifo_size __func__.51623 __func__.51457 chv_set_memory_pm5 valleyview_set_rps __warned.57640 gen6_set_rps intel_print_wm_latency __func__.54383 __intel_rps_boost_work __func__.61792 __gen6_update_ring_freq __func__.61725 gen6_init_rps_frequencies gen6_enable_rps __func__.58633 __func__.59305 __func__.59405 __warned.59412 __warned.59312 intel_read_wm_latency chv_set_memory_dvfs __func__.56815 single_enabled_crtc i845_update_wm i845_wm_info __func__.53469 i965_update_wm __func__.53110 pineview_update_wm pineview_display_wm pineview_cursor_wm pineview_display_hplloff_wm pineview_cursor_hplloff_wm __func__.51875 i9xx_update_wm i945_wm_info i830_a_wm_info i915_wm_info i830_bc_wm_info __func__.53218 vlv_update_wm __func__.52951 skl_update_pipe_wm skl_update_other_pipe_wm ilk_wm_merge ilk_update_wm skl_update_wm i915_mch_dev __i915_chipset_val cparams __func__.57084 __i915_update_gfx_val __i915_gfx_val __func__.59101 __func__.57980 __func__.59168 __func__.59224 __func__.59061 __warned.59225 ilk_increase_wm_latency.clone.0 g4x_update_wm __func__.61350 __func__.54455 __func__.51292 g4x_compute_wm0.clone.1 __func__.52058 __func__.53023 __ksymtab_i915_gpu_turbo_disable __kstrtab_i915_gpu_turbo_disable __kcrctab_i915_gpu_turbo_disable __ksymtab_i915_gpu_busy __kstrtab_i915_gpu_busy __kcrctab_i915_gpu_busy __ksymtab_i915_gpu_lower __kstrtab_i915_gpu_lower __kcrctab_i915_gpu_lower __ksymtab_i915_gpu_raise __kstrtab_i915_gpu_raise __kcrctab_i915_gpu_raise __ksymtab_i915_read_mch_val __kstrtab_i915_read_mch_val __kcrctab_i915_read_mch_val .LC2 intel_runtime_pm.c hsw_power_well_enabled gen9_set_dc_state_debugmask_memory_up skl_power_well_enabled i9xx_always_on_power_well_noop i9xx_always_on_power_well_enabled __func__.51464 __func__.51450 __func__.53934 __func__.53989 __func__.51753 __key.53671 vlv_power_wells skl_power_wells hsw_power_wells bdw_power_wells i9xx_always_on_power_well bxt_power_wells chv_power_wells __func__.53643 vlv_power_well_enabled chv_pipe_power_well_enabled assert_chv_phy_status __func__.53286 vlv_set_power_well vlv_dpio_cmn_power_well_disable __warned.52904 vlv_power_well_disable vlv_power_well_enable chv_dpio_cmn_power_well_disable __warned.53180 __func__.53185 vlv_power_well_sync_hw chv_set_pipe_power_well chv_pipe_power_well_sync_hw __warned.53472 vlv_dpio_cmn_power_well_enable __warned.52878 vlv_display_power_well_deinit vlv_display_power_well_disable __warned.52857 chv_pipe_power_well_disable __warned.53516 vlv_display_power_well_init vlv_display_power_well_enable __warned.52836 chv_pipe_power_well_enable __warned.53495 __func__.53321 chv_dpio_cmn_power_well_enable __warned.53086 __func__.53103 skl_set_power_well __func__.52283 __warned.52191 __warned.52042 __warned.51799 __warned.51792 __func__.52007 __warned.51826 __warned.51821 __warned.51816 __warned.52035 __func__.52217 __warned.52064 __warned.52059 __func__.52231 skl_power_well_disable skl_power_well_enable skl_power_well_sync_hw hsw_set_power_well __func__.51593 hsw_power_well_disable hsw_power_well_enable hsw_power_well_sync_hw i9xx_always_on_power_well_ops hsw_power_well_ops skl_power_well_ops chv_pipe_power_well_ops chv_dpio_cmn_power_well_ops vlv_display_power_well_ops vlv_dpio_power_well_ops vlv_dpio_cmn_power_well_ops .LC35 i915_ioc32.c i915_compat_ioctls compat_i915_getparam i915_debugfs.c obj_rank_by_stolen i915_fbc_fc_get i915_wedged_get i915_ring_stop_get i915_ring_missed_irq_get i915_ring_test_irq_get i915_drop_caches_get i915_dpcd_fops i915_dpcd_open i915_dpcd_show i915_displayport_test_active_open i915_displayport_test_active_show i915_displayport_test_type_open i915_displayport_test_type_show i915_displayport_test_data_open i915_displayport_test_data_show cur_wm_latency_open cur_wm_latency_show spr_wm_latency_open spr_wm_latency_show pri_wm_latency_open pri_wm_latency_show display_crc_ctl_open display_crc_ctl_show i915_dpcd_debug pipe_crc_sources i915_llc i915_frontbuffer_tracking i915_hws_info i915_ring_seqno_info i915_capabilities i915_pipe_crc_data i915_debugfs_list i915_forcewake_fops i915_debugfs_files i915_runtime_pm_status per_file_ctx i915_displayport_test_active_write __func__.57077 i915_fbc_fc_fops_open i915_fbc_fc_set i915_next_seqno_fops_open i915_next_seqno_set i915_next_seqno_get i915_drop_caches_fops_open i915_drop_caches_set i915_ring_test_irq_fops_open i915_ring_test_irq_set i915_ring_missed_irq_fops_open i915_ring_missed_irq_set i915_ring_stop_fops_open i915_ring_stop_set i915_cache_sharing_fops_open i915_cache_sharing_set i915_cache_sharing_get i915_min_freq_fops_open i915_min_freq_set i915_min_freq_get i915_max_freq_fops_open i915_max_freq_set i915_max_freq_get i915_wedged_fops_open i915_wedged_set i915_power_domain_info wm_latency_show i9xx_pipe_crc_auto_source i915_ddb_info i915_shared_dplls_info wm_latency_write cur_wm_latency_write spr_wm_latency_write pri_wm_latency_write i915_pipe_crc_release i915_pipe_crc_open i915_drrs_status hsw_trans_edp_pipe_A_crc_wa display_crc_ctl_write __func__.56989 __func__.56710 __func__.57031 __func__.56902 __func__.57788 __func__.57721 i915_error_state_release i915_error_state_open i915_error_state_write __func__.52529 i915_error_state_read __func__.57821 __func__.58087 i915_wa_registers i915_energy_uJ i915_swizzle_info CSWTCH.1429 i915_sr_status i915_ips_status __func__.57986 __func__.57900 i915_forcewake_release i915_forcewake_open i915_rps_boost_info i915_guc_info i915_interrupt_info i915_gem_seqno_info i915_gem_request_info cherryview_sseu_device_status gen9_sseu_device_status i915_sseu_status i915_dp_mst_info i915_semaphore_status i915_sink_crc i915_edp_psr_status i915_ppgtt_info i915_forcewake_domains i915_execlists per_file_stats print_batch_pool_stats describe_obj CSWTCH.1427 i915_context_status i915_gem_framebuffer_info i915_gem_batch_pool_info i915_gem_fence_regs_info i915_gem_object_list_info i915_opregion i915_fbc_status i915_ring_freq_table i915_emon_status i915_drpc_info i915_hangcheck_info i915_frequency_info i915_guc_load_status_info i915_gem_pageflip_info i915_gem_stolen_list_info i915_gem_gtt_info i915_gem_object_info drm_add_fake_info_node i915_pipe_crc_fops i915_pipe_crc_read __key.58734 intel_seq_print_mode.clone.0 intel_panel_info i915_display_info i915_guc_log_dump i915_dump_lrc i915_wedged_fops i915_max_freq_fops i915_min_freq_fops i915_cache_sharing_fops i915_ring_stop_fops i915_ring_missed_irq_fops i915_ring_test_irq_fops i915_drop_caches_fops i915_error_state_fops i915_next_seqno_fops i915_display_crc_ctl_fops i915_pri_wm_latency_fops i915_spr_wm_latency_fops i915_cur_wm_latency_fops i915_fbc_fc_fops i915_displayport_test_data_fops i915_displayport_test_type_fops i915_displayport_test_active_fops i915_cmd_parser.c gen7_blt_get_cmd_length_mask __func__.51137 gen7_bsd_get_cmd_length_mask __func__.51115 gen7_render_get_cmd_length_mask __func__.51094 vmap_batch __func__.52062 __func__.52327 __func__.52192 __func__.52114 fini_hash_table gen7_render_cmds hsw_render_ring_cmds gen7_render_regs ivb_master_regs gen7_blt_cmds hsw_blt_ring_cmds gen7_blt_regs hsw_master_regs hsw_vebox_cmds gen7_video_cmds common_cmds render_cmds hsw_render_cmds video_cmds blt_cmds hsw_blt_cmds vecs_cmds .LC12 i915_gem_batch_pool.c .LC4 i915_gem_context.c context_idr_cleanup intel_ring_emit __func__.51863 __func__.52076 i915_gem_create_context __func__.51304 __func__.52042 __func__.51403 i915_gem_debug.c i915_gem_dmabuf.c i915_gem_dmabuf_kmap_atomic i915_gem_dmabuf_kunmap_atomic i915_gem_dmabuf_kmap i915_gem_dmabuf_kunmap i915_gem_dmabuf_mmap i915_gem_object_put_pages_dmabuf i915_gem_dmabuf_vunmap i915_gem_object_get_pages_dmabuf i915_gem_dmabuf_vmap i915_gem_begin_cpu_access i915_gem_unmap_dma_buf i915_gem_map_dma_buf i915_dmabuf_ops i915_gem_object_dmabuf_ops .LC0 .LC1 i915_gem_evict.c mark_free i915_gem_execbuffer.c i915_gem_object_get_page i915_gem_execbuffer_reserve_vma i915_gem_execbuffer_unreserve_vma i915_gem_execbuffer_reserve clflush_write32 eb_lookup_vmas __func__.51106 __func__.52416 __func__.52331 i915_gem_execbuffer_relocate_entry __warned.51446 __warned.51434 __func__.51439 i915_gem_execbuffer_relocate_vma i915_gem_do_execbuffer __func__.52226 __func__.52587 __func__.52128 __func__.52903 __func__.52816 i915_gem_fence.c i915_gem_write_fence i915_gem_object_update_fence i915_gem_object_wait_fence i915_gem_gtt.c ppgtt_bind_vma ppgtt_unbind_vma byt_pte_encode hsw_pte_encode iris_pte_encode kmap_page_dma ggtt_unbind_vma i915_gtt_color_adjust bdw_setup_private_ppat chv_setup_private_ppat get_pd_offset vgpu_mm_switch gen6_mm_switch __warned.55455 gen8_ggtt_clear_range snb_pte_encode __func__.51284 ivb_pte_encode __func__.51310 __i915_gem_vma_create i915_ggtt_flush i915_gmch_probe i915_gmch_remove gen6_gmch_probe gen6_gmch_remove gen8_gmch_probe __func__.54893 __func__.51114 __pdp_fini free_gen8_temp_bitmaps gen8_ppgtt_notify_vgt __setup_page_dma alloc_scratch_page ggtt_probe_common gen8_ggtt_insert_entries ggtt_bind_vma gen6_ggtt_clear_range gen6_ggtt_insert_entries alloc_pd rotate_pages i915_get_ggtt_vma_pages __warned.55346 __func__.55259 aliasing_gtt_bind_vma cleanup_page_dma free_scratch_page free_pt gen6_free_scratch free_pd free_pdp gen8_free_scratch i915_ggtt_insert_entries i915_ggtt_clear_range i915_address_space_init kunmap_page_dma fill_page_dma gen6_initialize_pt gen6_ppgtt_insert_entries gen6_ppgtt_clear_range gen8_ppgtt_clear_pte_range gen8_ppgtt_clear_range gen8_ppgtt_insert_pte_entries gen6_dump_ppgtt gen8_dump_pdp gen8_dump_ppgtt gen6_ppgtt_cleanup gen8_ppgtt_cleanup_3lvl gen8_ppgtt_cleanup gen8_ppgtt_alloc_page_directories gen8_ppgtt_insert_entries __func__.53924 __func__.53744 gen8_write_pdp gen8_legacy_mm_switch gen8_48b_mm_switch gen7_mm_switch hsw_mm_switch __pdp_init alloc_pdp alloc_gen8_temp_bitmaps alloc_pt __hw_ppgtt_init gen8_alloc_va_range __func__.53533 gen6_alloc_va_range __func__.53615 __func__.54400 gen8_alloc_va_range_3lvl .LC63 i915_gem.c init_unused_ring trace_i915_gem_object_change_domain drm_gem_object_unreference __func__.58170 i915_gem_retire_work_handler i915_gem_idle_work_handler __key.58035 __key.58048 __key.58049 i915_gem_object_get_pages_gtt i915_gem_object_truncate i915_gem_wait_for_error __func__.54940 i915_set_reset_status __func__.55194 i915_gem_object_ops fake_irq shmem_clflush_swizzled_range i915_gem_object_release_phys i915_gem_object_get_pages_phys __warned.57245 i915_gem_request_retire i915_gem_object_retire__write i915_gem_object_flush_cpu_write_domain drm_gem_object_unreference_unlocked i915_gem_create i915_gem_object_retire__read i915_gem_object_flush_active i915_gem_object_retire_request i915_gem_object_wait_rendering__nonblocking i915_gem_object_put_pages_gtt i915_gem_object_put_pages_phys __func__.54701 i915_gem_init_seqno __func__.57931 __i915_vma_unbind i915_gem_object_do_pin __func__.55955 __warned.56872 __warned.54462 __func__.56201 i915_gem_phys_ops .LC19 .LC21 i915_gem_render_state.c CSWTCH.795 i915_gem_shrinker.c i915_gem_shrinker_scan i915_gem_shrinker_count i915_gem_shrinker_oom i915_gem_shrinker_lock i915_gem_stolen.c i915_gem_object_get_pages_stolen i915_gem_object_put_pages_stolen _i915_gem_object_create_stolen i915_gem_object_stolen_ops __func__.51630 __key.51503 __func__.51524 __func__.51438 __func__.51414 CSWTCH.847 __func__.51130 __func__.51752 i915_gem_object_release_stolen __func__.51714 .LC20 i915_gem_tiling.c i915_gem_userptr.c __key.53694 __i915_gem_userptr_set_active __i915_mm_struct_free __i915_mm_struct_free__worker cancel_userptr i915_gem_userptr_put_pages __i915_gem_userptr_set_pages i915_gem_userptr_mn_invalidate_range_start i915_gem_userptr_init__mmu_notifier __cancel_userptr__worker i915_gem_userptr_notifier i915_gem_userptr_ops i915_gem_userptr_dmabuf_export drm_malloc_ab.clone.0 __i915_gem_userptr_get_pages_worker i915_gem_userptr_get_pages i915_gem_userptr_release i915_gpu_error.c i915_error_state_free i915_error_object_free capture_bo i915_error_object_create __i915_error_ok __i915_error_advance i915_error_puts i915_error_vprintf print_error_buffers CSWTCH.935 CSWTCH.937 print_error_obj CSWTCH.939 __func__.52980 CSWTCH.941 warned.52976 i915_trace_points.c event_i915_pipe_update_start __warned.54014 ftrace_raw_output_i915_pipe_update_vblank_evaded event_i915_pipe_update_vblank_evaded __warned.54080 ftrace_raw_output_i915_pipe_update_end event_i915_pipe_update_end __warned.54146 ftrace_raw_output_i915_gem_object_create event_i915_gem_object_create __warned.54210 ftrace_raw_output_i915_gem_shrink event_i915_gem_shrink __warned.54272 ftrace_raw_output_i915_vma_bind event_i915_vma_bind __warned.54335 ftrace_raw_output_i915_vma_unbind event_i915_vma_unbind __warned.54407 ftrace_raw_output_i915_va_alloc event_i915_va_alloc __warned.54471 ftrace_raw_output_i915_page_table_entry_alloc event_i915_page_table_entry_alloc __warned.54539 ftrace_raw_output_i915_page_directory_entry_alloc event_i915_page_directory_entry_alloc __warned.54601 ftrace_raw_output_i915_page_directory_pointer_entry_alloc event_i915_page_directory_pointer_entry_alloc __warned.54657 ftrace_raw_output_i915_page_table_entry_map event_i915_page_table_entry_map __warned.54715 ftrace_raw_output_i915_gem_object_change_domain event_i915_gem_object_change_domain __warned.54784 ftrace_raw_output_i915_gem_object_pwrite event_i915_gem_object_pwrite __warned.54851 ftrace_raw_output_i915_gem_object_pread event_i915_gem_object_pread __warned.54914 ftrace_raw_output_i915_gem_object_fault event_i915_gem_object_fault __warned.54977 ftrace_raw_output_id_i915_gem_object __warned.55049 ftrace_raw_output_i915_gem_object_clflush event_i915_gem_object_clflush ftrace_raw_output_i915_gem_object_destroy event_i915_gem_object_destroy ftrace_raw_output_i915_gem_evict event_i915_gem_evict __warned.55117 ftrace_raw_output_i915_gem_evict_everything event_i915_gem_evict_everything __warned.55188 ftrace_raw_output_i915_gem_evict_vm event_i915_gem_evict_vm __warned.55249 ftrace_raw_output_i915_gem_ring_sync_to event_i915_gem_ring_sync_to __warned.55311 ftrace_raw_output_i915_gem_ring_dispatch event_i915_gem_ring_dispatch __warned.55375 ftrace_raw_output_i915_gem_ring_flush event_i915_gem_ring_flush __warned.55439 ftrace_raw_output_id_i915_gem_request __warned.55503 ftrace_raw_output_i915_gem_request_add event_i915_gem_request_add ftrace_raw_output_i915_gem_request_retire event_i915_gem_request_retire ftrace_raw_output_i915_gem_request_complete event_i915_gem_request_complete ftrace_raw_output_i915_gem_request_wait_end event_i915_gem_request_wait_end ftrace_raw_output_i915_gem_request_notify event_i915_gem_request_notify __warned.55566 ftrace_raw_output_i915_gem_request_wait_begin event_i915_gem_request_wait_begin __warned.55643 ftrace_raw_output_i915_flip_request event_i915_flip_request __warned.55718 ftrace_raw_output_i915_flip_complete event_i915_flip_complete __warned.55780 ftrace_raw_output_intel_gpu_freq_change event_intel_gpu_freq_change __warned.55842 ftrace_raw_output_id_i915_ppgtt __warned.55903 ftrace_raw_output_i915_ppgtt_create event_i915_ppgtt_create ftrace_raw_output_i915_ppgtt_release event_i915_ppgtt_release ftrace_raw_output_id_i915_context __warned.55972 ftrace_raw_output_i915_context_create event_i915_context_create ftrace_raw_output_i915_context_free event_i915_context_free ftrace_raw_output_switch_mm event_switch_mm __warned.56042 ftrace_profile_disable_i915_pipe_update_start ftrace_profile_i915_pipe_update_start ftrace_raw_unreg_event_i915_pipe_update_start ftrace_raw_event_i915_pipe_update_start ftrace_profile_disable_i915_pipe_update_vblank_evaded ftrace_profile_i915_pipe_update_vblank_evaded ftrace_raw_unreg_event_i915_pipe_update_vblank_evaded ftrace_raw_event_i915_pipe_update_vblank_evaded ftrace_profile_disable_i915_pipe_update_end ftrace_profile_i915_pipe_update_end ftrace_raw_unreg_event_i915_pipe_update_end ftrace_raw_event_i915_pipe_update_end ftrace_profile_disable_i915_gem_object_create ftrace_profile_i915_gem_object_create ftrace_raw_unreg_event_i915_gem_object_create ftrace_raw_event_i915_gem_object_create ftrace_profile_disable_i915_gem_shrink ftrace_profile_i915_gem_shrink ftrace_raw_unreg_event_i915_gem_shrink ftrace_raw_event_i915_gem_shrink ftrace_profile_disable_i915_vma_bind ftrace_profile_i915_vma_bind ftrace_raw_unreg_event_i915_vma_bind ftrace_raw_event_i915_vma_bind ftrace_profile_disable_i915_vma_unbind ftrace_profile_i915_vma_unbind ftrace_raw_unreg_event_i915_vma_unbind ftrace_raw_event_i915_vma_unbind ftrace_profile_disable_i915_va_alloc ftrace_profile_i915_va_alloc ftrace_raw_unreg_event_i915_va_alloc ftrace_raw_event_i915_va_alloc ftrace_profile_disable_i915_page_table_entry_alloc ftrace_profile_i915_page_table_entry_alloc ftrace_raw_unreg_event_i915_page_table_entry_alloc ftrace_raw_event_i915_page_table_entry_alloc ftrace_profile_disable_i915_page_directory_entry_alloc ftrace_profile_i915_page_directory_entry_alloc ftrace_raw_unreg_event_i915_page_directory_entry_alloc ftrace_raw_event_i915_page_directory_entry_alloc ftrace_profile_disable_i915_page_directory_pointer_entry_alloc ftrace_profile_i915_page_directory_pointer_entry_alloc ftrace_raw_unreg_event_i915_page_directory_pointer_entry_alloc ftrace_raw_event_i915_page_directory_pointer_entry_alloc ftrace_profile_disable_i915_page_table_entry_map ftrace_profile_i915_page_table_entry_map ftrace_raw_unreg_event_i915_page_table_entry_map ftrace_raw_event_i915_page_table_entry_map ftrace_profile_disable_i915_gem_object_change_domain ftrace_profile_i915_gem_object_change_domain ftrace_raw_unreg_event_i915_gem_object_change_domain ftrace_raw_event_i915_gem_object_change_domain ftrace_profile_disable_i915_gem_object_pwrite ftrace_profile_i915_gem_object_pwrite ftrace_raw_unreg_event_i915_gem_object_pwrite ftrace_raw_event_i915_gem_object_pwrite ftrace_profile_disable_i915_gem_object_pread ftrace_profile_i915_gem_object_pread ftrace_raw_unreg_event_i915_gem_object_pread ftrace_raw_event_i915_gem_object_pread ftrace_profile_disable_i915_gem_object_fault ftrace_profile_i915_gem_object_fault ftrace_raw_unreg_event_i915_gem_object_fault ftrace_raw_event_i915_gem_object_fault ftrace_profile_disable_i915_gem_object_clflush ftrace_profile_i915_gem_object_clflush ftrace_raw_unreg_event_i915_gem_object_clflush ftrace_raw_event_i915_gem_object_clflush ftrace_profile_disable_i915_gem_object_destroy ftrace_profile_i915_gem_object_destroy ftrace_raw_unreg_event_i915_gem_object_destroy ftrace_raw_event_i915_gem_object_destroy ftrace_profile_disable_i915_gem_evict ftrace_profile_i915_gem_evict ftrace_raw_unreg_event_i915_gem_evict ftrace_raw_event_i915_gem_evict ftrace_profile_disable_i915_gem_evict_everything ftrace_profile_i915_gem_evict_everything ftrace_raw_unreg_event_i915_gem_evict_everything ftrace_raw_event_i915_gem_evict_everything ftrace_profile_disable_i915_gem_evict_vm ftrace_profile_i915_gem_evict_vm ftrace_raw_unreg_event_i915_gem_evict_vm ftrace_raw_event_i915_gem_evict_vm ftrace_profile_disable_i915_gem_ring_sync_to ftrace_profile_i915_gem_ring_sync_to ftrace_raw_unreg_event_i915_gem_ring_sync_to ftrace_raw_event_i915_gem_ring_sync_to ftrace_profile_disable_i915_gem_ring_dispatch ftrace_profile_i915_gem_ring_dispatch ftrace_raw_unreg_event_i915_gem_ring_dispatch ftrace_raw_event_i915_gem_ring_dispatch ftrace_profile_disable_i915_gem_ring_flush ftrace_profile_i915_gem_ring_flush ftrace_raw_unreg_event_i915_gem_ring_flush ftrace_raw_event_i915_gem_ring_flush ftrace_profile_disable_i915_gem_request_add ftrace_profile_i915_gem_request_add ftrace_raw_unreg_event_i915_gem_request_add ftrace_raw_event_i915_gem_request_add ftrace_profile_disable_i915_gem_request_notify ftrace_profile_i915_gem_request_notify ftrace_raw_unreg_event_i915_gem_request_notify ftrace_raw_event_i915_gem_request_notify ftrace_profile_disable_i915_gem_request_retire ftrace_profile_i915_gem_request_retire ftrace_raw_unreg_event_i915_gem_request_retire ftrace_raw_event_i915_gem_request_retire ftrace_profile_disable_i915_gem_request_complete ftrace_profile_i915_gem_request_complete ftrace_raw_unreg_event_i915_gem_request_complete ftrace_raw_event_i915_gem_request_complete ftrace_profile_disable_i915_gem_request_wait_begin ftrace_profile_i915_gem_request_wait_begin ftrace_raw_unreg_event_i915_gem_request_wait_begin ftrace_raw_event_i915_gem_request_wait_begin ftrace_profile_disable_i915_gem_request_wait_end ftrace_profile_i915_gem_request_wait_end ftrace_raw_unreg_event_i915_gem_request_wait_end ftrace_raw_event_i915_gem_request_wait_end ftrace_profile_disable_i915_flip_request ftrace_profile_i915_flip_request ftrace_raw_unreg_event_i915_flip_request ftrace_raw_event_i915_flip_request ftrace_profile_disable_i915_flip_complete ftrace_profile_i915_flip_complete ftrace_raw_unreg_event_i915_flip_complete ftrace_raw_event_i915_flip_complete ftrace_profile_disable_intel_gpu_freq_change ftrace_profile_intel_gpu_freq_change ftrace_raw_unreg_event_intel_gpu_freq_change ftrace_raw_event_intel_gpu_freq_change ftrace_profile_disable_i915_ppgtt_create ftrace_profile_i915_ppgtt_create ftrace_raw_unreg_event_i915_ppgtt_create ftrace_raw_event_i915_ppgtt_create ftrace_profile_disable_i915_ppgtt_release ftrace_profile_i915_ppgtt_release ftrace_raw_unreg_event_i915_ppgtt_release ftrace_raw_event_i915_ppgtt_release ftrace_profile_disable_i915_context_create ftrace_profile_i915_context_create ftrace_raw_unreg_event_i915_context_create ftrace_raw_event_i915_context_create ftrace_profile_disable_i915_context_free ftrace_profile_i915_context_free ftrace_raw_unreg_event_i915_context_free ftrace_raw_event_i915_context_free ftrace_profile_disable_switch_mm ftrace_profile_switch_mm ftrace_raw_unreg_event_switch_mm ftrace_raw_event_switch_mm ftrace_profile_enable_i915_pipe_update_start ftrace_raw_reg_event_i915_pipe_update_start ftrace_profile_enable_i915_pipe_update_vblank_evaded ftrace_raw_reg_event_i915_pipe_update_vblank_evaded ftrace_profile_enable_i915_pipe_update_end ftrace_raw_reg_event_i915_pipe_update_end ftrace_profile_enable_i915_gem_object_create ftrace_raw_reg_event_i915_gem_object_create ftrace_profile_enable_i915_gem_shrink ftrace_raw_reg_event_i915_gem_shrink ftrace_profile_enable_i915_vma_bind ftrace_raw_reg_event_i915_vma_bind ftrace_profile_enable_i915_vma_unbind ftrace_raw_reg_event_i915_vma_unbind ftrace_profile_enable_i915_va_alloc ftrace_raw_reg_event_i915_va_alloc ftrace_profile_enable_i915_page_table_entry_alloc ftrace_raw_reg_event_i915_page_table_entry_alloc ftrace_profile_enable_i915_page_directory_entry_alloc ftrace_raw_reg_event_i915_page_directory_entry_alloc ftrace_profile_enable_i915_page_directory_pointer_entry_alloc ftrace_raw_reg_event_i915_page_directory_pointer_entry_alloc ftrace_profile_enable_i915_page_table_entry_map ftrace_raw_reg_event_i915_page_table_entry_map ftrace_profile_enable_i915_gem_object_change_domain ftrace_raw_reg_event_i915_gem_object_change_domain ftrace_profile_enable_i915_gem_object_pwrite ftrace_raw_reg_event_i915_gem_object_pwrite ftrace_profile_enable_i915_gem_object_pread ftrace_raw_reg_event_i915_gem_object_pread ftrace_profile_enable_i915_gem_object_fault ftrace_raw_reg_event_i915_gem_object_fault ftrace_profile_enable_i915_gem_object_clflush ftrace_raw_reg_event_i915_gem_object_clflush ftrace_profile_enable_i915_gem_object_destroy ftrace_raw_reg_event_i915_gem_object_destroy ftrace_profile_enable_i915_gem_evict ftrace_raw_reg_event_i915_gem_evict ftrace_profile_enable_i915_gem_evict_everything ftrace_raw_reg_event_i915_gem_evict_everything ftrace_profile_enable_i915_gem_evict_vm ftrace_raw_reg_event_i915_gem_evict_vm ftrace_profile_enable_i915_gem_ring_sync_to ftrace_raw_reg_event_i915_gem_ring_sync_to ftrace_profile_enable_i915_gem_ring_dispatch ftrace_raw_reg_event_i915_gem_ring_dispatch ftrace_profile_enable_i915_gem_ring_flush ftrace_raw_reg_event_i915_gem_ring_flush ftrace_profile_enable_i915_gem_request_add ftrace_raw_reg_event_i915_gem_request_add ftrace_profile_enable_i915_gem_request_notify ftrace_raw_reg_event_i915_gem_request_notify ftrace_profile_enable_i915_gem_request_retire ftrace_raw_reg_event_i915_gem_request_retire ftrace_profile_enable_i915_gem_request_complete ftrace_raw_reg_event_i915_gem_request_complete ftrace_profile_enable_i915_gem_request_wait_begin ftrace_raw_reg_event_i915_gem_request_wait_begin ftrace_profile_enable_i915_gem_request_wait_end ftrace_raw_reg_event_i915_gem_request_wait_end ftrace_profile_enable_i915_flip_request ftrace_raw_reg_event_i915_flip_request ftrace_profile_enable_i915_flip_complete ftrace_raw_reg_event_i915_flip_complete ftrace_profile_enable_intel_gpu_freq_change ftrace_raw_reg_event_intel_gpu_freq_change ftrace_profile_enable_i915_ppgtt_create ftrace_raw_reg_event_i915_ppgtt_create ftrace_profile_enable_i915_ppgtt_release ftrace_raw_reg_event_i915_ppgtt_release ftrace_profile_enable_i915_context_create ftrace_raw_reg_event_i915_context_create ftrace_profile_enable_i915_context_free ftrace_raw_reg_event_i915_context_free ftrace_profile_enable_switch_mm ftrace_raw_reg_event_switch_mm ftrace_define_fields_i915_pipe_update_start ftrace_define_fields_i915_pipe_update_vblank_evaded ftrace_define_fields_i915_pipe_update_end ftrace_define_fields_i915_gem_object_create ftrace_define_fields_i915_gem_shrink ftrace_define_fields_i915_vma_bind ftrace_define_fields_i915_vma_unbind ftrace_define_fields_i915_va ftrace_define_fields_i915_px_entry ftrace_define_fields_i915_page_table_entry_update ftrace_define_fields_i915_gem_object_change_domain ftrace_define_fields_i915_gem_object_pwrite ftrace_define_fields_i915_gem_object_pread ftrace_define_fields_i915_gem_object_fault ftrace_define_fields_i915_gem_object ftrace_define_fields_i915_gem_evict ftrace_define_fields_i915_gem_evict_everything ftrace_define_fields_i915_gem_evict_vm ftrace_define_fields_i915_gem_ring_sync_to ftrace_define_fields_i915_gem_ring_dispatch ftrace_define_fields_i915_gem_ring_flush ftrace_define_fields_i915_gem_request_notify ftrace_define_fields_i915_gem_request_wait_begin ftrace_define_fields_i915_gem_request ftrace_define_fields_i915_flip_request ftrace_define_fields_i915_flip_complete ftrace_define_fields_intel_gpu_freq_change ftrace_define_fields_i915_ppgtt ftrace_define_fields_i915_context ftrace_define_fields_switch_mm ftrace_raw_init_event_i915_pipe_update_start ftrace_event_type_i915_pipe_update_start ftrace_raw_init_event_i915_pipe_update_vblank_evaded ftrace_event_type_i915_pipe_update_vblank_evaded ftrace_raw_init_event_i915_pipe_update_end ftrace_event_type_i915_pipe_update_end ftrace_raw_init_event_i915_gem_object_create ftrace_event_type_i915_gem_object_create ftrace_raw_init_event_i915_gem_shrink ftrace_event_type_i915_gem_shrink ftrace_raw_init_event_i915_vma_bind ftrace_event_type_i915_vma_bind ftrace_raw_init_event_i915_vma_unbind ftrace_event_type_i915_vma_unbind ftrace_raw_init_event_i915_va_alloc ftrace_event_type_i915_va_alloc ftrace_raw_init_event_i915_page_table_entry_alloc ftrace_event_type_i915_page_table_entry_alloc ftrace_raw_init_event_i915_page_directory_entry_alloc ftrace_event_type_i915_page_directory_entry_alloc ftrace_raw_init_event_i915_page_directory_pointer_entry_alloc ftrace_event_type_i915_page_directory_pointer_entry_alloc ftrace_raw_init_event_i915_page_table_entry_map ftrace_event_type_i915_page_table_entry_map ftrace_raw_init_event_i915_gem_object_change_domain ftrace_event_type_i915_gem_object_change_domain ftrace_raw_init_event_i915_gem_object_pwrite ftrace_event_type_i915_gem_object_pwrite ftrace_raw_init_event_i915_gem_object_pread ftrace_event_type_i915_gem_object_pread ftrace_raw_init_event_i915_gem_object_fault ftrace_event_type_i915_gem_object_fault ftrace_raw_init_event_i915_gem_object_clflush ftrace_event_type_i915_gem_object_clflush ftrace_raw_init_event_i915_gem_object_destroy ftrace_event_type_i915_gem_object_destroy ftrace_raw_init_event_i915_gem_evict ftrace_event_type_i915_gem_evict ftrace_raw_init_event_i915_gem_evict_everything ftrace_event_type_i915_gem_evict_everything ftrace_raw_init_event_i915_gem_evict_vm ftrace_event_type_i915_gem_evict_vm ftrace_raw_init_event_i915_gem_ring_sync_to ftrace_event_type_i915_gem_ring_sync_to ftrace_raw_init_event_i915_gem_ring_dispatch ftrace_event_type_i915_gem_ring_dispatch ftrace_raw_init_event_i915_gem_ring_flush ftrace_event_type_i915_gem_ring_flush ftrace_raw_init_event_i915_gem_request_add ftrace_event_type_i915_gem_request_add ftrace_raw_init_event_i915_gem_request_notify ftrace_event_type_i915_gem_request_notify ftrace_raw_init_event_i915_gem_request_retire ftrace_event_type_i915_gem_request_retire ftrace_raw_init_event_i915_gem_request_complete ftrace_event_type_i915_gem_request_complete ftrace_raw_init_event_i915_gem_request_wait_begin ftrace_event_type_i915_gem_request_wait_begin ftrace_raw_init_event_i915_gem_request_wait_end ftrace_event_type_i915_gem_request_wait_end ftrace_raw_init_event_i915_flip_request ftrace_event_type_i915_flip_request ftrace_raw_init_event_i915_flip_complete ftrace_event_type_i915_flip_complete ftrace_raw_init_event_intel_gpu_freq_change ftrace_event_type_intel_gpu_freq_change ftrace_raw_init_event_i915_ppgtt_create ftrace_event_type_i915_ppgtt_create ftrace_raw_init_event_i915_ppgtt_release ftrace_event_type_i915_ppgtt_release ftrace_raw_init_event_i915_context_create ftrace_event_type_i915_context_create ftrace_raw_init_event_i915_context_free ftrace_event_type_i915_context_free ftrace_raw_init_event_switch_mm ftrace_event_type_switch_mm ftrace_raw_event_id_i915_px_entry ftrace_raw_event_id_i915_gem_object ftrace_raw_event_id_i915_gem_request ftrace_raw_event_id_i915_ppgtt ftrace_raw_event_id_i915_context ftrace_profile_templ_i915_gem_ring_sync_to.clone.21 ftrace_profile_templ_i915_flip_request.clone.26 ftrace_profile_templ_i915_flip_complete.clone.27 ftrace_profile_templ_i915_gem_ring_dispatch.clone.22 ftrace_profile_templ_i915_gem_ring_flush.clone.23 ftrace_profile_templ_i915_gem_request_notify.clone.24 ftrace_profile_templ_i915_gem_request_wait_begin.clone.25 ftrace_profile_templ_intel_gpu_freq_change.clone.28 ftrace_profile_templ_i915_px_entry ftrace_profile_templ_i915_gem_object ftrace_profile_templ_i915_gem_request ftrace_profile_templ_i915_ppgtt ftrace_profile_templ_i915_context ftrace_profile_templ_switch_mm.clone.0 ftrace_profile_templ_i915_pipe_update_start.clone.5 ftrace_profile_templ_i915_pipe_update_vblank_evaded.clone.6 ftrace_profile_templ_i915_pipe_update_end.clone.7 ftrace_profile_templ_i915_gem_object_create.clone.8 ftrace_profile_templ_i915_gem_shrink.clone.9 ftrace_profile_templ_i915_vma_bind.clone.10 ftrace_profile_templ_i915_vma_unbind.clone.11 ftrace_profile_templ_i915_va.clone.12 __warned.60123 ftrace_profile_templ_i915_page_table_entry_update.clone.13 ftrace_profile_templ_i915_gem_object_change_domain.clone.14 ftrace_profile_templ_i915_gem_object_pwrite.clone.15 ftrace_profile_templ_i915_gem_object_pread.clone.16 ftrace_profile_templ_i915_gem_object_fault.clone.17 ftrace_profile_templ_i915_gem_evict.clone.18 ftrace_profile_templ_i915_gem_evict_everything.clone.19 ftrace_profile_templ_i915_gem_evict_vm.clone.20 __tpstrtab_i915_pipe_update_start __tpstrtab_i915_pipe_update_vblank_evaded __tpstrtab_i915_pipe_update_end __tpstrtab_i915_gem_object_create __tpstrtab_i915_gem_shrink __tpstrtab_i915_vma_bind __tpstrtab_i915_vma_unbind __tpstrtab_i915_va_alloc __tpstrtab_i915_page_table_entry_alloc __tpstrtab_i915_page_directory_entry_alloc __tpstrtab_i915_page_directory_pointer_entry_alloc __tpstrtab_i915_page_table_entry_map __tpstrtab_i915_gem_object_change_domain __tpstrtab_i915_gem_object_pwrite __tpstrtab_i915_gem_object_pread __tpstrtab_i915_gem_object_fault __tpstrtab_i915_gem_object_clflush __tpstrtab_i915_gem_object_destroy __tpstrtab_i915_gem_evict __tpstrtab_i915_gem_evict_everything __tpstrtab_i915_gem_evict_vm __tpstrtab_i915_gem_ring_sync_to __tpstrtab_i915_gem_ring_dispatch __tpstrtab_i915_gem_ring_flush __tpstrtab_i915_gem_request_add __tpstrtab_i915_gem_request_notify __tpstrtab_i915_gem_request_retire __tpstrtab_i915_gem_request_complete __tpstrtab_i915_gem_request_wait_begin __tpstrtab_i915_gem_request_wait_end __tpstrtab_i915_flip_request __tpstrtab_i915_flip_complete __tpstrtab_intel_gpu_freq_change __tpstrtab_i915_ppgtt_create __tpstrtab_i915_ppgtt_release __tpstrtab_i915_context_create __tpstrtab_i915_context_free __tpstrtab_switch_mm __event_switch_mm __event_i915_context_free __event_i915_context_create __event_i915_ppgtt_release __event_i915_ppgtt_create __event_intel_gpu_freq_change __event_i915_flip_complete __event_i915_flip_request __event_i915_gem_request_wait_end __event_i915_gem_request_wait_begin __event_i915_gem_request_complete __event_i915_gem_request_retire __event_i915_gem_request_notify __event_i915_gem_request_add __event_i915_gem_ring_flush __event_i915_gem_ring_dispatch __event_i915_gem_ring_sync_to __event_i915_gem_evict_vm __event_i915_gem_evict_everything __event_i915_gem_evict __event_i915_gem_object_destroy __event_i915_gem_object_clflush __event_i915_gem_object_fault __event_i915_gem_object_pread __event_i915_gem_object_pwrite __event_i915_gem_object_change_domain __event_i915_page_table_entry_map __event_i915_page_directory_pointer_entry_alloc __event_i915_page_directory_entry_alloc __event_i915_page_table_entry_alloc __event_i915_va_alloc __event_i915_vma_unbind __event_i915_vma_bind __event_i915_gem_shrink __event_i915_gem_object_create __event_i915_pipe_update_end __event_i915_pipe_update_vblank_evaded __event_i915_pipe_update_start print_fmt_switch_mm print_fmt_i915_context print_fmt_i915_ppgtt print_fmt_intel_gpu_freq_change print_fmt_i915_flip_complete print_fmt_i915_flip_request print_fmt_i915_gem_request print_fmt_i915_gem_request_wait_begin print_fmt_i915_gem_request_notify print_fmt_i915_gem_ring_flush print_fmt_i915_gem_ring_dispatch print_fmt_i915_gem_ring_sync_to print_fmt_i915_gem_evict_vm print_fmt_i915_gem_evict_everything print_fmt_i915_gem_evict print_fmt_i915_gem_object print_fmt_i915_gem_object_fault print_fmt_i915_gem_object_pread print_fmt_i915_gem_object_pwrite print_fmt_i915_gem_object_change_domain print_fmt_i915_page_table_entry_update print_fmt_i915_page_directory_pointer_entry_alloc print_fmt_i915_page_directory_entry_alloc print_fmt_i915_px_entry print_fmt_i915_va print_fmt_i915_vma_unbind print_fmt_i915_vma_bind print_fmt_i915_gem_shrink print_fmt_i915_gem_object_create print_fmt_i915_pipe_update_end print_fmt_i915_pipe_update_vblank_evaded print_fmt_i915_pipe_update_start ftrace_raw_output_i915_pipe_update_start intel_lrc.c gen8_get_seqno gen8_set_seqno gen8_emit_flush_coherentl3_wa i915_page_dir_dma_addr intel_lr_context_do_pin gen8_logical_ring_put_irq gen8_logical_ring_get_irq execlists_check_remove_request bxt_a_set_seqno bxt_a_get_seqno gen8_emit_flush lrc_destroy_wa_ctx_obj __func__.54064 __func__.54335 logical_ring_init __key.53600 gen8_emit_bb_start gen8_emit_flush_render gen8_init_rcs_context __warned.52179 gen8_init_common_ring __func__.53169 gen8_init_render_ring gen9_init_render_ring execlists_update_context execlists_context_unqueue gen8_emit_request __func__.51905 __func__.53078 __func__.53035 .LC8 intel_mocs.c emit_mocs_control_table __func__.51136 skylake_mocs_table __func__.51181 broxton_mocs_table __warned.51066 intel_ringbuffer.c __intel_ring_advance ring_write_tail gen6_ring_get_seqno ring_get_seqno ring_set_seqno pc_render_get_seqno pc_render_set_seqno stop_ring gen6_bsd_ring_write_tail wa_add gen8_init_workarounds gen9_init_workarounds hsw_vebox_put_irq gen8_ring_put_irq gen8_ring_get_irq i9xx_ring_put_irq i9xx_ring_get_irq i8xx_ring_put_irq i8xx_ring_get_irq hsw_vebox_get_irq gen6_ring_put_irq gen5_ring_put_irq gen6_ring_get_irq gen5_ring_get_irq init_ring_common __func__.51612 CSWTCH.1097 init_render_ring render_ring_cleanup __func__.51777 intel_init_ring_buffer __key.54536 __func__.54363 gen6_ring_flush gen6_add_request gen8_ring_dispatch_execbuffer gen8_ring_sync gen8_xcs_signal gen6_ring_dispatch_execbuffer gen6_ring_sync gen6_signal gen6_bsd_ring_flush bsd_ring_flush i9xx_add_request i965_dispatch_execbuffer gen8_rcs_signal intel_rcs_ctx_init __func__.51823 hsw_ring_dispatch_execbuffer gen2_render_ring_flush gen4_render_ring_flush i915_dispatch_execbuffer gen8_emit_pipe_control gen8_render_ring_flush pc_render_add_request gen7_render_ring_flush gen6_render_ring_flush i830_dispatch_execbuffer intel_uncore.c fw_domains_put __intel_uncore_forcewake_get ironlake_do_reset i915_do_reset g4x_reset_complete g33_do_reset g4x_do_reset assert_device_not_suspended __warned.51207 gen2_read64 gen2_read32 gen2_read16 gen2_read8 gen2_write64 gen2_write32 gen2_write16 gen2_write8 gen5_read64 gen5_read32 gen5_read16 gen5_read8 gen5_write64 gen5_write32 gen5_write16 gen5_write8 gen6_gt_check_fifodbg fw_domains_put_with_fifo __gen6_gt_wait_for_fifo hsw_unclaimed_reg_debug forcewake_domain_names fw_domains_get fw_domains_get_with_thread_status fw_domain_init intel_uncore_fw_release_timer vgpu_read64 vgpu_read32 vgpu_read16 vgpu_read8 vgpu_write64 vgpu_write32 vgpu_write16 vgpu_write8 gen6_write64 gen6_write32 gen6_write16 gen6_write8 __force_wake_get __intel_uncore_forcewake_put gen8_do_reset gen6_do_reset hsw_unclaimed_reg_detect mmio_debug_once.52130 __func__.52131 hsw_write64 hsw_write32 hsw_write16 hsw_write8 __intel_uncore_early_sanitize gen9_write8 gen9_write16 gen9_write32 gen9_write64 gen9_read8 gen9_read16 gen9_read32 gen9_read64 chv_write8 chv_write16 chv_write32 chv_write64 chv_read8 chv_read16 chv_read32 chv_read64 vlv_read8 vlv_read16 vlv_read32 vlv_read64 gen8_write8 gen8_write16 gen8_write32 gen8_write64 gen6_read8 gen6_read16 gen6_read32 gen6_read64 gen8_shadowed_regs gen9_shadowed_regs intel_guc_loader.c CSWTCH.832 direct_interrupts_to_host __func__.51535 __func__.51608 guc_ucode_xfer_dma __func__.51263 __warned.51468 __func__.51333 __func__.51462 __mod_firmware63 i915_guc_submission.c host2guc_action guc_fini_ctx_desc gem_allocate_guc_obj guc_init_ctx_desc gem_release_guc_obj guc_client_free __func__.51397 __func__.51376 __func__.51781 intel_renderstate_gen6.c gen6_null_state_relocs gen6_null_state_batch intel_renderstate_gen7.c gen7_null_state_relocs gen7_null_state_batch intel_renderstate_gen8.c gen8_null_state_relocs gen8_null_state_batch intel_renderstate_gen9.c gen9_null_state_relocs gen9_null_state_batch intel_audio.c ilk_audio_codec_enable ilk_audio_codec_disable hsw_audio_codec_enable hsw_audio_codec_disable g4x_audio_codec_enable g4x_audio_codec_disable i915_audio_component_bind_ops i915_audio_component_unbind i915_audio_component_bind i915_audio_component_ops audio_config_hdmi_pixel_clock hdmi_audio_clock __func__.51332 __func__.51441 __func__.51475 i915_audio_component_sync_audio_rate aud_ncts __func__.52099 __func__.51537 __func__.51670 __func__.51758 i915_audio_component_get_power i915_audio_component_get_cdclk_freq __warned.52034 i915_audio_component_put_power i915_audio_component_codec_wake_override __func__.51584 __func__.51860 intel_atomic.c __func__.51308 intel_atomic_plane.c intel_plane_atomic_update __func__.51416 __func__.51401 intel_plane_atomic_check __func__.51306 intel_bios.c find_section intel_no_opregion_vbt_callback __func__.52404 validate_vbt __func__.52423 fill_detail_timing_data intel_no_opregion_vbt panel_type __func__.52279 __func__.51555 __func__.51338 __func__.51716 __func__.51453 __func__.51400 __func__.52026 __func__.51599 __func__.51801 mapping.51992 __func__.51891 __func__.51995 __func__.51518 __func__.52369 __func__.51685 intel_display.c CSWTCH.2897 intel_PLL_is_valid skl_detach_scaler intel_pipe_set_base_atomic ironlake_pch_transcoder_set_timings ironlake_pfit_enable ironlake_pfit_disable broxton_get_display_clock_speed broadwell_get_display_clock_speed haswell_get_display_clock_speed ilk_get_display_clock_speed i945_get_display_clock_speed i915_get_display_clock_speed i9xx_misc_get_display_clock_speed i865_get_display_clock_speed i830_get_display_clock_speed intel_cpu_transcoder_set_m_n intel_set_pipe_timings intel_get_pipe_timings intel_set_pipe_csc intel_cpu_transcoder_get_m_n hsw_read_dcomp intel_default_queue_flip intel_fuzzy_clock_check intel_compare_link_m_n update_scanline_offset ibx_pch_dpll_mode_set intel_commit_primary_plane intel_disable_primary_plane i915gm_get_display_clock_speed pnv_get_display_clock_speed i85x_get_display_clock_speed CSWTCH.2900 update_state_fb intel_pipe_config_compare __func__.71693 intel_hpll_vco elk_vco.63171 cl_vco.63170 pnv_vco.63169 blb_vco.63168 ctg_vco.63172 __func__.63188 g33_get_display_clock_speed div_3200.63344 div_4000.63345 div_5333.63347 div_4800.63346 i965gm_get_display_clock_speed div_4000.63309 div_3200.63308 div_5333.63310 gm45_get_display_clock_speed i9xx_set_pipeconf __func__.64774 intel_update_cdclk __func__.60917 __func__.61104 skl_update_scaler __func__.59233 __func__.59293 intel_pipe_will_have_type skylake_get_display_clock_speed i9xx_get_refclk __func__.63800 vlv_calc_dpll_params pnv_calc_dpll_params i9xx_calc_dpll_params i9xx_crtc_clock_get __func__.69230 cpt_set_fdi_bc_bifurcation __func__.58772 ironlake_get_pfit_config skylake_pfit_enable __func__.59400 vlv_PLL_is_optimal __warned.53339 __func__.59327 __func__.70617 port_to_aux_power_domain __func__.60532 __func__.60607 __warned.60595 port_to_power_domain __func__.60514 __warned.60546 __func__.57605 __func__.57587 __func__.57569 clear_intel_crtc_state vlv_find_best_dpll chv_find_best_dpll modeset_get_crtc_power_domains intel_crtc_disable_planes intel_dump_pipe_config __func__.71131 __func__.71103 ironlake_get_pipe_config haswell_get_pipe_config ibx_pch_dpll_get_hw_state ivb_manual_fdi_link_train snb_b_fdi_train_param __func__.58332 gen6_fdi_link_train __func__.58213 i915_disable_vga __func__.77009 check_wm_state intel_dmi_reverse_brightness quirk_backlight_present quirk_invert_brightness quirk_ssc_force_disable quirk_pipeb_force quirk_pipea_force assert_planes_disabled assert_sprites_disabled assert_fdi_tx assert_fdi_rx assert_pch_dp_disabled assert_pch_hdmi_disabled assert_pch_transcoder_disabled ibx_pch_dpll_disable ibx_pch_dpll_enable ironlake_fdi_link_train __func__.58139 i9xx_pfit_enable vlv_disable_pll intel_disable_shared_dpll __func__.55816 intel_enable_shared_dpll __func__.55759 intel_limit intel_limits_bxt intel_limits_i9xx_sdvo intel_limits_i9xx_lvds intel_limits_ironlake_dac intel_limits_ironlake_dual_lvds intel_limits_ironlake_dual_lvds_100m intel_limits_g4x_single_channel_lvds intel_limits_g4x_dual_channel_lvds intel_limits_vlv intel_limits_chv intel_limits_pineview_sdvo intel_limits_pineview_lvds intel_limits_g4x_hdmi intel_limits_g4x_sdvo intel_limits_ironlake_single_lvds intel_limits_ironlake_single_lvds_100m intel_limits_i8xx_lvds intel_limits_i8xx_dac intel_limits_i8xx_dvo i9xx_select_p2_div i9xx_find_best_dpll pnv_find_best_dpll g4x_find_best_dpll hsw_write_dcomp broadwell_modeset_commit_cdclk broxton_set_cdclk broxton_modeset_commit_cdclk __func__.61262 vlv_enable_pll vlv_get_cck_clock_hpll valleyview_get_display_clock_speed valleyview_modeset_commit_cdclk __func__.61647 assert_vblank_disabled __func__.57455 __func__.56394 __warned.56387 intel_fill_fb_ggtt_view i9xx_get_initial_plane_config __func__.65144 ironlake_get_initial_plane_config __func__.66833 skylake_get_initial_plane_config __func__.66701 i9xx_update_primary_plane ironlake_update_primary_plane pipe_dsl_stopped i9xx_get_pipe_config chv_disable_pll chv_prepare_pll chv_enable_pll vlv_prepare_pll lpt_disable_clkout_dp haswell_crtc_compute_clock intel_finish_crtc_commit intel_begin_crtc_commit __func__.57988 intel_crtc_atomic_check __func__.70917 __intel_pageflip_stall_check __func__.73454 page_flip_completed i915_gem_request_assign intel_unpin_fb_obj __warned.56668 intel_crtc_destroy intel_check_primary_plane intel_check_cursor_plane __func__.74060 intel_framebuffer_init __func__.75475 intel_fb_funcs intel_user_framebuffer_dirty intel_user_framebuffer_create_handle __func__.75385 __warned.70215 do_intel_finish_page_flip skl_cdclk_frequencies __func__.61412 __func__.58956 ironlake_crtc_compute_clock __func__.66397 __func__.65970 __warned.58604 skylake_update_primary_plane __func__.56585 __warned.56576 intel_crtc_page_flip intel_unpin_work_fn intel_mmio_flip_work_func __func__.70290 __func__.73666 intel_modeset_setup_plane_state.clone.0 assert_dsi_pll.clone.1 assert_cursor.clone.2 intel_disable_pipe __func__.56306 i9xx_crtc_disable __func__.62197 ironlake_crtc_disable haswell_crtc_disable intel_enable_pipe __func__.56207 assert_plane.clone.3 intel_pre_disable_primary intel_crtc_disable_noatomic intel_crtc_load_lut intel_crtc_gamma_set i9xx_crtc_enable valleyview_crtc_enable ironlake_crtc_enable __func__.55717 haswell_crtc_enable __func__.58674 intel_pre_plane_update intel_atomic_commit __func__.73364 __func__.72811 __func__.72637 __func__.72527 __func__.62448 i9xx_update_pll_dividers.clone.4 i9xx_crtc_compute_clock lpt_init_pch_refclk __func__.65597 __func__.67583 __func__.67556 compute_m_n intel_crtc_update_cursor __func__.68569 __warned.68148 intel_disable_cursor_plane intel_commit_cursor_plane broxton_modeset_calc_cdclk valleyview_modeset_calc_cdclk broadwell_modeset_calc_cdclk __func__.69134 intel_gen3_queue_flip intel_gen2_queue_flip intel_gen4_queue_flip intel_gen6_queue_flip intel_gen7_queue_flip __warned.69884 intel_user_framebuffer_destroy intel_atomic_check __func__.71479 __func__.62625 __func__.73217 __func__.62741 __func__.71004 intel_framebuffer_create intel_user_framebuffer_create intel_framebuffer_create_for_mode.clone.9 load_detect_mode __func__.69006 intel_modeset_setup_hw_state __func__.76794 __func__.76954 __func__.77085 __func__.77253 __func__.70006 intel_alloc_initial_plane_obj __func__.56781 intel_mode_funcs intel_quirks intel_dmi_quirks __key.75810 skl_primary_formats i8xx_primary_formats i965_primary_formats intel_cursor_formats intel_crtc_funcs ibx_pch_dpll_names __func__.52480 intel_helper_funcs __func__.75000 __func__.76459 __func__.74629 __compound_literal.0 .LC91 .LC271 intel_fbc.c i8xx_fbc_enabled g4x_fbc_enabled intel_fbc_nuke ilk_fbc_enabled __key.52451 g4x_fbc_enable g4x_fbc_disable gen7_fbc_enable ilk_fbc_disable ilk_fbc_enable i8xx_fbc_enable i8xx_fbc_disable __func__.51069 __func__.51248 __func__.51351 __func__.51216 __func__.51396 __func__.51293 __func__.51631 set_no_fbc_reason __func__.51643 intel_fbc_work_fn intel_fbc_cancel_work __func__.51531 __intel_fbc_disable __intel_fbc_cleanup_cfb __intel_fbc_update __func__.51850 __print_once.51851 __func__.52220 intel_fifo_underrun.c intel_frontbuffer.c intel_frontbuffer_flush intel_hotplug.c i915_hotplug_work_func i915_digport_work_func intel_hpd_irq_storm_reenable_work __func__.51172 __func__.51303 __func__.51217 __warned.51363 __func__.51071 __func__.51362 intel_modes.c broadcast_rgb_names force_audio_names intel_overlay.c check_gamma_bounds intel_overlay_map_regs update_polyphase_filter y_static_hcoeffs uv_static_hcoeffs update_reg_attrs __func__.52393 intel_overlay_release_old_vid_tail intel_overlay_off_tail intel_overlay_recover_from_interrupt intel_overlay_do_wait_request intel_overlay_release_old_vid __func__.51242 __func__.52181 intel_psr.c intel_psr_write_vsc intel_psr_work __key.52299 intel_psr_activate intel_psr_exit __func__.51557 __func__.51370 aux_msg.51142 intel_sideband.c vlv_sideband_rw.clone.0 __func__.51067 intel_sprite.c skl_disable_plane vlv_disable_plane ivb_disable_plane ilk_disable_plane intel_commit_sprite_plane vlv_update_plane vlv_plane_formats intel_check_sprite_plane ilk_update_plane ilk_plane_formats snb_plane_formats skl_update_plane skl_plane_formats ivb_update_plane __func__.52174 __func__.51254 intel_acpi.c intel_dsm_platform_mux_info intel_dsm_priv intel_dsm_guid __func__.51461 CSWTCH.793 intel_dsm.clone.0 __func__.51379 intel_dsm_detect __func__.51527 __func__.51556 intel_opregion.c swsci __print_once.51455 __func__.51456 asle_work __func__.52204 __func__.52257 power_state_map __func__.51854 __func__.51816 __func__.51798 __func__.51833 __func__.51669 __func__.51757 __func__.51733 __func__.51709 __func__.51721 __func__.51745 intel_opregion_notifier system_opregion intel_opregion_video_event get_did set_did __func__.52053 CSWTCH.871 __warned.51580 intel_fbdev.c intel_crtc_fb_gamma_set intel_crtc_fb_gamma_get __func__.51738 intel_fbdev_suspend_worker intel_fb_initial_config __func__.51329 intel_fbdev_pan_display intel_fbdev_blank intel_fbdev_set_par intel_fb_helper_funcs intelfb_alloc intelfb_create intelfb_ops __func__.51171 dvo_ch7017.c ch7017_mode_valid ch7017_read ch7017_dump_regs __func__.51238 ch7017_get_hw_state ch7017_write ch7017_destroy ch7017_dpms ch7017_mode_set __func__.51175 ch7017_init __func__.51129 ch7017_detect dvo_ch7xxx.c ch7xxx_readb ch7xxx_dump_regs ch7xxx_get_hw_state ch7xxx_writeb __func__.51166 ch7xxx_detect ch7xxx_mode_set ch7xxx_dpms ch7xxx_destroy ch7xxx_init ch7xxx_ids ch7xxx_dids __func__.51196 ch7xxx_mode_valid dvo_ivch.c ivch_mode_valid ivch_read ivch_dump_regs ivch_write __func__.51143 ivch_reset backup_addresses __func__.51226 ivch_get_hw_state ivch_mode_set ivch_destroy ivch_dpms ivch_init __func__.51174 ivch_detect dvo_ns2501.c ns2501_destroy ns2501_readb __func__.51127 ns2501_get_hw_state ns2501_writeb __func__.51157 ns2501_mode_set ns2501_modes mode_agnostic_values __func__.51253 ns2501_mode_valid __func__.51221 ns2501_dpms ns2501_init __func__.51184 ns2501_detect dvo_sil164.c sil164_mode_set sil164_readb __func__.51098 sil164_dump_regs __func__.51239 sil164_get_hw_state sil164_detect sil164_dpms __func__.51128 sil164_destroy sil164_init __func__.51155 sil164_mode_valid dvo_tfp410.c tfp410_mode_set tfp410_readb tfp410_dump_regs __func__.51257 tfp410_get_hw_state tfp410_detect tfp410_getid tfp410_dpms tfp410_destroy tfp410_init tfp410_mode_valid intel_crt.c intel_crt_set_dpms intel_disable_crt pch_disable_crt pch_post_disable_crt intel_enable_crt intel_crt_compute_config intel_crt_set_property intel_crt_mode_valid intel_crt_reset __func__.52441 intel_crt_get_edid __func__.52095 intel_crt_ddc_get_modes intel_crt_get_modes intel_crt_detect_ddc intel_crt_destroy intel_crt_detect __func__.52309 __func__.51998 __func__.51907 __func__.51821 __func__.52188 intel_no_crt_dmi_callback intel_no_crt intel_crt_connector_funcs intel_crt_enc_funcs hsw_crt_get_config intel_crt_connector_helper_funcs intel_crt_get_config intel_crt_get_hw_state intel_ddi.c hsw_ddi_wrpll_disable hsw_ddi_spll_disable skl_ddi_pll_disable skl_dpll_regs broxton_phy_uninit bxt_ddi_pll_disable intel_ddi_destroy intel_ddi_funcs intel_ddi_compute_config intel_enable_ddi intel_ddi_pre_enable intel_disable_ddi intel_ddi_post_disable __func__.54980 hsw_ddi_spll_enable hsw_ddi_wrpll_enable intel_wait_ddi_buf_idle bxt_ddi_vswing_sequence bxt_ddi_translations_hdmi bxt_ddi_translations_edp bxt_ddi_translations_dp __func__.53252 skl_y_ddi_translations_hdmi skl_ddi_translations_hdmi skl_y_ddi_translations_dp skl_u_ddi_translations_dp skl_ddi_translations_dp skl_ddi_translations_edp skl_y_ddi_translations_edp skl_u_ddi_translations_edp __func__.53395 intel_ddi_get_crtc_encoder hsw_ddi_calc_wrpll_link ddi_get_encoder_port skl_ddi_pll_get_hw_state bxt_ddi_pll_get_hw_state __func__.54503 hsw_ddi_spll_get_hw_state hsw_ddi_wrpll_get_hw_state bxt_ddi_pll_enable skl_ddi_pll_enable broxton_phy_init skl_ddi_pll_names bxt_ddi_pll_names __func__.53081 dividers.52496 __func__.52524 __func__.52281 __func__.52571 bxt_dp_clk_val __func__.52649 ddi_dotclock_get __func__.54857 hsw_ddi_translations_dp hsw_ddi_translations_hdmi hsw_ddi_translations_fdi bdw_ddi_translations_dp bdw_ddi_translations_hdmi bdw_ddi_translations_fdi bdw_ddi_translations_edp even_dividers.52491 odd_dividers.52492 intel_dp_mst.c intel_dp_mst_enc_get_hw_state intel_dp_mst_set_property intel_dp_mst_mode_valid intel_mst_atomic_best_encoder intel_mst_best_encoder intel_dp_mst_get_hw_state intel_dp_mst_hotplug intel_dp_mst_connector_destroy intel_dp_destroy_mst_connector __func__.51892 intel_dp_register_mst_connector intel_dp_add_mst_connector intel_dp_mst_connector_funcs intel_dp_mst_connector_helper_funcs intel_dp_mst_get_modes intel_dp_mst_detect intel_dp_mst_encoder_destroy mst_cbs intel_dp_mst_enc_funcs intel_dp_mst_compute_config intel_mst_disable_dp intel_mst_post_disable_dp intel_mst_pre_enable_dp intel_mst_enable_dp intel_dp_mst_enc_get_config __func__.51597 __func__.51546 __func__.51481 intel_dp.c vlv_pipe_has_pp_on vlv_pipe_has_vdd_on vlv_pipe_any vlv_initial_pps_pipe vlv_get_aux_clock_divider skl_get_aux_clock_divider i9xx_get_aux_send_ctl skl_get_aux_send_ctl intel_dp_source_rates skl_rates default_rates bxt_rates intel_dp_prepare port_mapping.57838 intel_dp_dpcd_read_wake intel_dp_probe_oui __func__.56649 intel_dp_probe_mst __func__.56679 __func__.54350 pps_lock intel_dp_link_down __func__.56426 vlv_post_disable_dp intel_dp_sink_rates intel_dp_common_rates intel_dp_mode_valid ilk_get_aux_clock_divider hsw_get_aux_clock_divider CSWTCH.1498 intel_dp_init_panel_power_sequencer_registers vlv_power_sequencer_pipe __func__.58215 vlv_steal_power_sequencer intel_dp_init_panel_power_sequencer vlv_dpll chv_dpll __func__.51660 _pp_ctrl_reg edp_have_panel_vdd ironlake_get_pp_control __func__.57928 _pp_stat_reg edp_panel_vdd_off_sync __func__.53949 vlv_detach_power_sequencer __func__.55111 __func__.55143 edp_have_panel_power vlv_initial_power_sequencer_setup __func__.51923 i9xx_get_aux_clock_divider edp_panel_vdd_schedule_off intel_edp_panel_vdd_sanitize __func__.57690 pps_unlock intel_dp_encoder_reset edp_notify_handler edp_panel_vdd_work ilk_post_disable_dp g4x_pre_enable_dp __func__.53513 __func__.54281 _intel_dp_set_link_train __func__.58569 _intel_edp_backlight_off wait_panel_status __func__.53708 __func__.54139 __func__.53778 edp_panel_vdd_off vlv_dp_pre_pll_enable chv_data_lane_soft_reset chv_post_disable_dp chv_dp_post_pll_disable chv_dp_pre_pll_enable intel_dp_encoder_suspend intel_dp_get_config __func__.54518 intel_dp_get_hw_state __func__.54394 intel_dp_get_modes intel_dp_set_edid intel_dp_force __func__.57508 intel_dp_connector_destroy intel_dp_set_property intel_dp_set_link_train intel_dp_set_drrs_state __func__.58417 intel_edp_drrs_downclock_work intel_dp_connector_unregister __func__.57188 __func__.57237 __func__.57163 __func__.57211 __func__.57265 intel_dp_sink_crc_stop __func__.56719 __func__.56793 intel_dp_set_signal_levels CSWTCH.1496 __func__.55983 __func__.55948 __func__.55927 intel_dp_update_link_train CSWTCH.1486 CSWTCH.1488 CSWTCH.1490 CSWTCH.1494 CSWTCH.1492 __func__.54233 gen4_dpll pch_dpll __func__.53278 intel_dp_reset_link_train.clone.0 intel_dp_link_training_clock_recovery __func__.56255 __func__.56352 intel_dp_check_mst_status __func__.56957 snprintf_int_array.clone.1 intel_dp_print_rates __func__.53170 intel_dp_get_dpcd __func__.56540 intel_dp_detect_dpcd __func__.57083 intel_dp_detect __func__.57431 __func__.56909 __func__.56866 intel_dp_connector_funcs intel_dp_connector_helper_funcs CSWTCH.1515 intel_dp_aux_transfer __func__.58918 __key.58724 __func__.58727 intel_edp_backlight_power __func__.58789 __func__.52701 intel_dp_enc_funcs intel_disable_dp vlv_pre_enable_dp vlv_enable_dp g4x_enable_dp chv_pre_enable_dp intel_dp_check_link_status __func__.57017 __func__.57742 _intel_edp_backlight_on __func__.54251 __func__.54199 wait_panel_power_cycle __func__.53788 edp_panel_vdd_on __func__.53856 intel_dp_aux_ch last_status.52480 __func__.52191 __func__.52499 edp_panel_on __func__.53768 __func__.54052 intel_enable_dp __func__.55007 __func__.55193 .LC9 intel_dsi.c intel_dsi_host_attach intel_dsi_host_detach txbyteclkhs intel_dsi_detect intel_dsi_mode_valid __func__.53327 intel_dsi_enable_nop __func__.52784 intel_dsi_get_modes __func__.54031 intel_dsi_connector_destroy __func__.54056 intel_dsi_encoder_destroy intel_dsi_funcs intel_dsi_compute_config intel_dsi_pre_pll_enable intel_dsi_pre_enable intel_dsi_pre_disable intel_dsi_post_disable intel_dsi_get_hw_state intel_dsi_get_config intel_dsi_host_ops intel_dsi_connector_funcs intel_dsi_connector_helper_funcs __func__.54088 intel_dsi_host_transfer wait_for_dsi_fifo_empty __func__.53266 __func__.53107 __func__.53073 __func__.52828 __func__.52922 __func__.54012 __func__.53600 __func__.52269 dpi_send_cmd.clone.0 __func__.52286 __func__.52656 __func__.52717 __func__.52389 __func__.52796 intel_dsi_panel_vbt.c generic_exec_sequence exec_elem __func__.51797 seq_name vbt_panel_enable vbt_panel_prepare vbt_panel_unprepare vbt_panel_disable CSWTCH.824 CSWTCH.826 vbt_panel_funcs __func__.51912 vbt_panel_get_modes mipi_exec_gpio gtable mipi_exec_delay mipi_exec_send_packet __func__.51698 intel_dsi_pll.c __func__.51490 __func__.51506 lfsr_converts __func__.51433 __func__.51810 __func__.51392 __func__.51582 intel_dvo.c intel_dvo_connector_get_hw_state intel_dvo_get_hw_state intel_dvo_get_config intel_disable_dvo intel_enable_dvo intel_dvo_mode_valid intel_dvo_pre_enable intel_dvo_get_modes intel_dvo_destroy intel_dvo_detect __func__.51463 intel_dvo_enc_destroy intel_dvo_enc_funcs intel_dvo_devices intel_dvo_compute_config intel_dvo_connector_funcs intel_dvo_connector_helper_funcs intel_hdmi.c g4x_infoframe_enabled ibx_infoframe_enabled cpt_infoframe_enabled vlv_infoframe_enabled hsw_infoframe_enabled intel_hdmi_prepare vlv_enable_hdmi intel_disable_hdmi pch_post_disable_hdmi hdmi_port_clock_valid intel_hdmi_mode_valid intel_hdmi_pre_enable assert_hdmi_port_disabled intel_hdmi_set_gcp_infoframe g4x_infoframe_index g4x_infoframe_enable __func__.51454 cpt_write_infoframe ibx_write_infoframe g4x_write_infoframe vlv_write_infoframe hsw_dip_data_reg __func__.51487 hsw_infoframe_enable __func__.51469 hsw_write_infoframe intel_enable_hdmi_audio __func__.52535 g4x_enable_hdmi ibx_enable_hdmi cpt_enable_hdmi vlv_hdmi_post_disable vlv_hdmi_pre_pll_enable chv_hdmi_post_disable vlv_hdmi_pre_enable chv_hdmi_post_pll_disable chv_hdmi_pre_enable chv_hdmi_pre_pll_enable intel_hdmi_get_config intel_hdmi_get_hw_state g4x_disable_hdmi pch_disable_hdmi intel_hdmi_get_modes intel_hdmi_set_edid intel_hdmi_force __func__.53121 intel_hdmi_destroy intel_hdmi_set_property intel_hdmi_detect __func__.53083 intel_hdmi_connector_funcs intel_hdmi_connector_helper_funcs __func__.53664 vlv_set_infoframes g4x_set_infoframes hsw_set_infoframes cpt_set_infoframes ibx_set_infoframes intel_hdmi_enc_funcs intel_write_infoframe intel_hdmi_set_avi_infoframe intel_hdmi_set_spd_infoframe intel_hdmi_set_hdmi_infoframe __func__.51935 __func__.52948 intel_i2c.c gmbus_pins_skl gmbus_pins gmbus_pins_bxt gmbus_pins_bdw intel_i2c_quirk_set get_reserved get_clock get_data set_clock set_data intel_gpio_post_xfer gmbus_func gmbus_wait_hw_status gmbus_xfer_read gmbus_wait_idle gmbus_xfer __func__.51711 __key.51811 __key.51812 gmbus_algorithm intel_gpio_pre_xfer intel_lvds.c intel_lvds_mode_valid intel_lvds_get_modes intel_lvds_destroy intel_lvds_set_property __func__.52395 intel_lvds_detect __func__.52293 intel_no_lvds_dmi_callback intel_dual_link_lvds_callback intel_no_modeset_on_lid_dmi_callback intel_no_lvds intel_lvds_connector_funcs intel_lvds_enc_funcs intel_enable_lvds intel_pre_enable_lvds intel_lvds_compute_config gmch_disable_lvds intel_lvds_get_hw_state intel_lvds_get_config intel_lvds_connector_helper_funcs intel_lid_notify __func__.52612 pch_disable_lvds pch_post_disable_lvds intel_dual_link_lvds intel_no_modeset_on_lid intel_disable_lvds __func__.52235 intel_panel.c centre_horizontally centre_vertically CSWTCH.957 lpt_get_backlight pch_get_backlight bxt_get_backlight lpt_set_backlight pch_set_backlight bxt_set_backlight spt_hz_to_pwm lpt_hz_to_pwm i965_hz_to_pwm vlv_setup_backlight vlv_enable_backlight vlv_disable_backlight vlv_set_backlight vlv_get_backlight vlv_hz_to_pwm lpt_setup_backlight lpt_enable_backlight lpt_disable_backlight i9xx_setup_backlight i9xx_enable_backlight i9xx_disable_backlight i9xx_set_backlight i9xx_get_backlight i9xx_hz_to_pwm bxt_setup_backlight bxt_enable_backlight bxt_disable_backlight pch_setup_backlight pch_enable_backlight pch_disable_backlight pch_hz_to_pwm i965_setup_backlight i965_enable_backlight i965_disable_backlight scale intel_panel_compute_brightness _vlv_get_backlight intel_panel_actually_set_backlight __func__.51788 __func__.52077 get_backlight_max_vbt __func__.52559 get_backlight_min_vbt __func__.52597 __func__.52140 __func__.52182 __func__.51866 __func__.51993 intel_backlight_device_update_status __func__.52318 intel_panel_get_backlight __func__.51653 intel_backlight_device_ops __func__.52374 intel_backlight_device_get_brightness __func__.52931 __func__.52276 __func__.51965 __func__.52037 intel_sdvo.c intel_sdvo_write_sdvox pch_disable_sdvo intel_sdvo_mode_valid intel_sdvo_ddc_proxy_func intel_sdvo_enc_destroy intel_sdvo_debug_write sdvo_cmd_names intel_sdvo_write_cmd __func__.51921 intel_sdvo_ddc_proxy_xfer intel_sdvo_enable_hotplug intel_sdvo_read_byte __func__.51813 intel_sdvo_read_response cmd_status_names __func__.52000 intel_sdvo_get_value intel_sdvo_connector_get_hw_state intel_sdvo_get_hw_state intel_sdvo_set_value intel_disable_sdvo pch_post_disable_sdvo intel_sdvo_set_timing intel_sdvo_connector_alloc intel_sdvo_connector_init intel_sdvo_connector_funcs intel_sdvo_connector_helper_funcs intel_sdvo_connector_unregister intel_sdvo_analog_init __func__.54166 intel_sdvo_destroy intel_sdvo_get_analog_edid intel_sdvo_get_modes sdvo_tv_modes __func__.53574 __func__.53486 __func__.53401 __func__.53514 intel_sdvo_set_property intel_sdvo_detect __func__.53424 intel_sdvo_dvi_init __func__.54087 intel_sdvo_create_enhance_property __func__.54406 __func__.54717 __func__.54762 intel_sdvo_tv_init tv_format_names __func__.54131 intel_sdvo_lvds_init __func__.54196 intel_sdvo_ddc_proxy intel_sdvo_enc_funcs intel_sdvo_compute_config intel_sdvo_pre_enable intel_enable_sdvo intel_sdvo_get_config __func__.54833 __func__.54227 __func__.53232 CSWTCH.962 __func__.53008 __func__.53166 intel_sdvo_get_dtd_from_mode intel_sdvo_set_output_timings_from_mode intel_sdvo_get_mode_from_dtd intel_sdvo_get_preferred_input_mode __func__.52651 intel_sdvo_set_avi_infoframe __func__.52496 intel_tv.c intel_tv_get_hw_state intel_disable_tv intel_tv_get_config intel_tv_mode_find tv_modes intel_tv_mode_valid intel_tv_compute_config __func__.51632 intel_tv_get_modes input_res_table intel_tv_destroy intel_tv_set_property intel_tv_detect reported_modes __func__.51952 __func__.52050 intel_enable_tv __func__.52302 intel_tv_connector_funcs intel_tv_enc_funcs intel_tv_pre_enable intel_tv_connector_helper_funcs hdtv_csc_yprpb sdtv_csc_yprpb component_levels ntsc_m_levels_composite ntsc_m_levels_svideo ntsc_m_csc_composite ntsc_m_csc_svideo filter_table ntsc_j_levels_composite ntsc_j_levels_svideo ntsc_j_csc_composite ntsc_j_csc_svideo pal_m_levels_composite pal_m_levels_svideo pal_m_csc_composite pal_m_csc_svideo pal_n_levels_composite pal_n_levels_svideo pal_n_csc_composite pal_n_csc_svideo pal_levels_composite pal_levels_svideo pal_csc_composite pal_csc_svideo i915_vgpu.c vgt_balloon_space bl_info __func__.51134 i915_dma.c i915_gem_reject_pin_ioctl i915_getparam __func__.52316 intel_teardown_mchbar broadwell_sseu_info_init __key.53513 __key.53517 __key.53518 __key.53519 __key.53520 i915_vga_set_decode i915_switcheroo_ops __func__.52810 __func__.52490 __func__.53255 i915_switcheroo_can_switch i915_switcheroo_set_state i915.mod.c _rheldata __mod_srcversion785 __mod_alias783 __mod_alias782 __mod_alias781 __mod_alias780 __mod_alias779 __mod_alias778 __mod_alias777 __mod_alias776 __mod_alias775 __mod_alias774 __mod_alias773 __mod_alias772 __mod_alias771 __mod_alias770 __mod_alias769 __mod_alias768 __mod_alias767 __mod_alias766 __mod_alias765 __mod_alias764 __mod_alias763 __mod_alias762 __mod_alias761 __mod_alias760 __mod_alias759 __mod_alias758 __mod_alias757 __mod_alias756 __mod_alias755 __mod_alias754 __mod_alias753 __mod_alias752 __mod_alias751 __mod_alias750 __mod_alias749 __mod_alias748 __mod_alias747 __mod_alias746 __mod_alias745 __mod_alias744 __mod_alias743 __mod_alias742 __mod_alias741 __mod_alias740 __mod_alias739 __mod_alias738 __mod_alias737 __mod_alias736 __mod_alias735 __mod_alias734 __mod_alias733 __mod_alias732 __mod_alias731 __mod_alias730 __mod_alias729 __mod_alias728 __mod_alias727 __mod_alias726 __mod_alias725 __mod_alias724 __mod_alias723 __mod_alias722 __mod_alias721 __mod_alias720 __mod_alias719 __mod_alias718 __mod_alias717 __mod_alias716 __mod_alias715 __mod_alias714 __mod_alias713 __mod_alias712 __mod_alias711 __mod_alias710 __mod_alias709 __mod_alias708 __mod_alias707 __mod_alias706 __mod_alias705 __mod_alias704 __mod_alias703 __mod_alias702 __mod_alias701 __mod_alias700 __mod_alias699 __mod_alias698 __mod_alias697 __mod_alias696 __mod_alias695 __mod_alias694 __mod_alias693 __mod_alias692 __mod_alias691 __mod_alias690 __mod_alias689 __mod_alias688 __mod_alias687 __mod_alias686 __mod_alias685 __mod_alias684 __mod_alias683 __mod_alias682 __mod_alias681 __mod_alias680 __mod_alias679 __mod_alias678 __mod_alias677 __mod_alias676 __mod_alias675 __mod_alias674 __mod_alias673 __mod_alias672 __mod_alias671 __mod_alias670 __mod_alias669 __mod_alias668 __mod_alias667 __mod_alias666 __mod_alias665 __mod_alias664 __mod_alias663 __mod_alias662 __mod_alias661 __mod_alias660 __mod_alias659 __mod_alias658 __mod_alias657 __mod_alias656 __mod_alias655 __mod_alias654 __mod_alias653 __mod_alias652 __mod_alias651 __mod_alias650 __mod_alias649 __mod_alias648 __mod_alias647 __mod_alias646 __mod_alias645 __mod_alias644 __mod_alias643 __mod_alias642 __mod_alias641 __mod_alias640 __mod_alias639 __mod_alias638 __mod_alias637 __mod_alias636 __mod_alias635 __mod_alias634 __mod_alias633 __mod_alias632 __mod_alias631 __mod_alias630 __mod_alias629 __module_depends ____versions __mod_vermagic5 register_shrinker2 intel_ddi_pll_select intel_guc_resume ns_to_timeval i915_gem_object_set_to_cpu_domain drm_framebuffer_cleanup drm_atomic_helper_plane_destroy_state i915_gem_fault drm_atomic_helper_check_modeset intel_plane_funcs drm_modeset_lock_crtc intel_ring_begin drm_dp_clock_recovery_ok drm_atomic_helper_check_planes gen6_enable_pm_irq strcpy pci_save_state drm_kms_helper_poll_fini intel_ddi_disable_transcoder_func intel_teardown_gmbus drm_open intel_attach_aspect_ratio_property bitmap_clear i915_capture_error_state i915_error_state_to_str drm_rgb_quant_range_selectable drm_mm_scan_remove_block drm_mode_vrefresh intel_dotclock_calculate i915_gem_track_fb intel_ring_space vscnprintf tracepoint_probe_unregister i915_guc_submission_disable vm_insert_pfn drm_fb_helper_single_add_all_connectors simple_attr_write ioread32 intel_mark_idle intel_get_load_detect_pipe drm_fb_helper_init intel_logical_ring_cleanup i915_vma_move_to_active intel_atomic_setup_scalers dma_ops intel_plane_atomic_get_property i915_gem_execbuffer i915_cmd_parser_fini_ring drm_poll intel_connector_get_hw_state intel_pm_setup queue_delayed_work intel_finish_page_flip_plane release_firmware drm_mode_object_find intel_ring_invalidate_all_caches i915_driver_unload intel_fbdev_set_suspend drm_kms_helper_poll_disable intel_panel_set_backlight_acpi __i915_vma_set_map_and_fenceable intel_ddi_disable_pipe_clock drm_mode_crtc_set_gamma_size intel_ring_idle simple_attr_open __intel_ring_space i915_gem_get_caching_ioctl intel_lr_context_reset dev_get_drvdata intel_ring_reserve_space i915_read_mch_val i915_cache_level_str i915_audio_component_init copy_from_user intel_init_bsd2_ring_buffer drm_mode_legacy_fb_format mod_timer_pinned broxton_uninit_cdclk intel_plane_atomic_set_property vlv_bunit_write drm_connector_register idr2_init drm_pick_cmdline_mode i915_gem_detect_bit_6_swizzle drm_fb_helper_fill_fix drm_dp_aux_register backlight_device_unregister i915_gem_object_save_bit_17_swizzle drm_dp_mst_detect_port intel_atomic_state_clear intel_hdmi_compute_config pci_set_consistent_dma_mask gen6_rps_idle intel_crtc_mode_get pci_enable_device i915_error_printf __tracepoint_switch_mm intel_pch_panel_fitting drm_dp_dpcd_read i915_gfx_val drm_panel_add intel_ddi_get_hw_state iowrite32 i915_gem_context_close i915_gem_batch_pool_fini intel_audio_codec_disable pcibios_align_resource intel_connector_unregister intel_init_vebox_ring_buffer drm_kms_helper_poll_init intel_encoder_destroy pm_qos_remove_requirement drm_mm_remove_node drm_ut_debug_printk intel_connector_attach_encoder drm_framebuffer_init bxt_get_dsi_pclk i915_gem_ringbuffer_submission drm_property_create intel_panel_setup_backlight i915_gem_cleanup_stolen skl_plane_ctl_rotation intel_sprite_set_colorkey drm_pci_init i915_gem_suspend_gtt_mappings i915_setup_sysfs intel_prepare_page_flip intel_irq_uninstall intel_modeset_gem_init pci_iomap drm_fb_helper_setcmap intel_fb_obj_flush drm_atomic_add_affected_planes memmove __this_module arch_phys_wc_del trace_seq_printf __pm_runtime_get intel_fbc_update i915_gem_object_alloc intel_prepare_plane_fb drm_modeset_unlock_all intel_runtime_pm_get hdmi_spd_infoframe_init pci_enable_msi_block snprintf intel_ddi_enable_transcoder_func copy_user_generic i915_gem_request_add_to_client drm_dp_update_payload_part2 drm_mode_probed_add drm_fb_helper_restore_fbdev_mode_unlocked i915_resume_switcheroo drm_atomic_add_affected_connectors vlv_cck_read intel_get_pipe_from_connector intel_frontbuffer_flip_complete bad_dma_address intel_hpd_init __symbol_put intel_dp_mst_suspend vm_get_page_prot i915_gem_context_setparam_ioctl pci_dev_put drm_atomic_helper_disable_plane i915_enable_pipestat sg_free_table intel_dp_sink_crc param_get_bool intel_disable_dsi_pll i915_gem_release __tracepoint_i915_vma_unbind drm_rect_calc_hscale gen6_update_ring_freq __bitmap_weight drm_crtc_vblank_count i915_gem_prime_import i915_gem_context_enable ivch_ops get_pid_task finish_wait drm_mm_takedown drm_modeset_lock_all find_first_bit drm_fb_helper_fini intel_attach_force_audio_property drm_debugfs_remove_files intel_display_capture_error_state sg_alloc_table_from_pages drm_fb_helper_remove_one_connector idr2_alloc intel_frontbuffer_flip_prepare request_firmware set_pages_uc drm_atomic_state_default_clear i915_gem_object_do_bit_17_swizzle __tracepoint_i915_gem_evict scnprintf put_page __tracepoint_i915_context_create intel_csr_load_status_get drm_atomic_helper_cleanup_planes i915_chipset_val i915_debugfs_connector_add vlv_force_pll_off i915_gem_create_ioctl __copy_from_user_inatomic drm_fb_helper_cfb_imageblit intel_ddc_get_modes __put_task_struct intel_edp_drrs_disable i915_switch_context intel_sbi_read mipi_dsi_create_packet intel_sdvo_init i915_debugfs_init ioremap_cache invalidate_mapping_pages drm_panel_detach drm_rect_clip_scaled compat_alloc_user_space vga_switcheroo_register_client i915_gem_obj_lookup_or_create_vma sysfs_create_bin_file iounmap i915_gem_batch_pool_get kref_get i915_semaphore_is_enabled i915_driver_postclose intel_edp_panel_off drm_get_subpixel_order_name intel_logical_rings_init i915_check_vgpu mod_delayed_work cleanup_module dma_supported nsecs_to_jiffies64 intel_uncore_check_errors i915_ppgtt_init_hw skip_spaces intel_ddi_clock_get intel_pch_rawclk pci_disable_msi prepare_to_wait vlv_gps_core_write i915_gem_get_tiling flush_scheduled_work vlv_ccu_write intel_cleanup_plane_fb i915_driver_open intel_fbc_disable memcpy component_del unmap_mapping_range i915_gem_init_hw drm_hdmi_avi_infoframe_from_display_mode i915_gem_context_create_ioctl intel_init_blt_ring_buffer i915_gem_object_ggtt_pin kstrtouint drm_helper_hpd_irq_event i915_gem_object_free vunmap skl_update_scaler_crtc i915_gem_context_destroy_ioctl ch7017_ops kfree i915_gem_request_cancel drm_mode_config_init ironlake_enable_display_irq i915_save_state drm_plane_helper_check_update __bitmap_empty i2c_bit_algo drm_atomic_helper_crtc_destroy_state kref_init __vmalloc i915_gem_object_create_stolen intel_opregion_asle_intr intel_csr_ucode_fini intel_lr_context_deferred_alloc drm_atomic_helper_commit_planes_on_crtc hsw_fdi_link_train intel_opregion_notify_adapter intel_runtime_pm_disable_interrupts getrawmonotonic i915_gem_gtt_prepare_object seq_lseek drm_edid_duplicate __tracepoint_i915_page_table_entry_map drm_crtc_cleanup __tracepoint_i915_gem_request_notify intel_edp_backlight_on i915_gem_shrinker_init i915_gem_context_free mipi_dsi_attach i915_ggtt_view_size warn_slowpath_fmt drm_get_format_name intel_modeset_cleanup pci_bus_write_config_byte __i915_vma_unbind_no_wait drm_gem_create_mmap_offset i915_gem_init_userptr do_gettimeofday intel_ddi_clk_select intel_atomic_get_shared_dpll_state bxt_enable_dc9 intel_frontbuffer_flip intel_gmch_remove i915_gem_context_fini intel_uncore_forcewake_get i915_gem_alloc_object ilk_wm_max_level intel_connector_update_modes intel_crt_init sysfs_remove_files pci_set_power_state drm_encoder_cleanup intel_ddi_init drm_gem_object_init intel_ddi_fdi_disable drm_connector_unregister intel_pin_and_fence_fb_obj i915_get_reset_stats_ioctl __wake_up drm_modeset_acquire_init assert_panel_unlocked intel_ring_reserved_space_cancel vsnprintf intel_digital_port_connected intel_sanitize_enable_execlists kmem_cache_create intel_dp_get_m_n intel_display_power_put drm_gem_prime_handle_to_fd dma_buf_attach gen5_disable_gt_irq drm_atomic_helper_connector_dpms i915_hotplug_interrupt_update intel_init_gt_powersave __per_cpu_offset __tracepoint_i915_pipe_update_start intel_fbc_enabled enc_to_intel_hdmi cpufreq_cpu_put i915_gem_obj_bound_any drm_detect_hdmi_monitor drm_fb_helper_alloc_fbi kmem_cache_alloc_trace i9xx_check_fifo_underruns __memcpy_fromio intel_get_crtc_scanline interval_tree_iter_first intel_display_power_well_is_enabled ilk_pipe_pixel_rate vlv_gpio_nc_write drm_panel_remove intel_get_shared_dpll intel_plane_duplicate_state intel_plane_init intel_fixed_panel_mode intel_stop_ring_buffer drm_format_plane_cpp init_module intel_set_cpu_fifo_underrun_reporting device_create_bin_file intel_uncore_init intel_tile_height __tracepoint_i915_gem_object_pread drm_mm_init_scan_with_range wake_up_process broxton_init_cdclk intel_init_pch_refclk drm_dp_mst_topology_mgr_init i915_ggtt_view_normal jiffies_to_usecs intel_best_encoder intel_set_pch_fifo_underrun_reporting i915_gem_request_free i915_update_gfx_val drm_fb_helper_hotplug_event intel_psr_flush intel_hrawclk i915_gpu_raise drm_pci_alloc drm_crtc_vblank_get drm_gem_object_lookup i915_guc_submit drm_dp_link_train_channel_eq_delay intel_overlay_put_image intel_lr_context_descriptor vlv_force_gfx_clock intel_finish_reset pv_cpu_ops acquire_console_sem vlv_get_dsi_pclk set_pages_wb drm_modeset_unlock_crtc acpi_target_system_state vlv_cck_write i915_gem_gtt_finish_object intel_gen4_compute_page_offset drm_mode_debug_printmodeline acpi_lid_notifier_register acpi_get_name release_console_sem tfp410_ops intel_uncore_fini drm_rect_rotate intel_gtt_insert_sg_entries i915 __devm_request_region ida2_destroy register_oom_notifier flush_delayed_work unregister_shrinker2 i915_gem_init_rings gen8_irq_power_well_post_enable drm_get_pci_dev per_cpu__ftrace_event_seq drm_irq_uninstall intel_ddi_connector_get_hw_state ch7xxx_ops vga_switcheroo_client_fb_set intel_init_render_ring_buffer i915_gem_render_state_prepare i915_gem_prime_export i915_needs_cmd_parser drm_dp_mst_get_edid intel_connector_init intel_lr_context_free intel_runtime_pm_get_noresume i915_gem_set_domain_ioctl intel_guc_ucode_init i915_error_state_buf_init intel_ddi_enable_pipe_clock drm_clflush_virt_range schedule_timeout schedule intel_gmbus_force_bit vlv_dpio_read drm_fb_helper_blank intel_pin_and_map_ringbuffer_obj i915_handle_error drm_dp_get_adjust_request_pre_emphasis intel_fbc_disable_crtc i915_gem_obj_prepare_shmem_read __tracepoint_i915_gem_evict_everything intel_pipe_update_end intel_link_compute_m_n drm_mode_create_aspect_ratio_property msecs_to_jiffies drm_gem_private_object_init drm_fb_helper_check_var ida2_simple_remove schedule_delayed_work get_user_pages intel_ring_init_seqno intel_init_pm intel_display_crc_init __stack_chk_fail drm_kms_helper_poll_enable_locked drm_crtc_vblank_reset i915_gem_get_seqno intel_dp_start_link_train intel_hpd_pin_to_port tracing_generic_entry_update intel_guc_ucode_fini intel_opregion_init i915_gem_obj_offset drm_framebuffer_unregister_private intel_ring_update_space __tracepoint_i915_gem_ring_dispatch i915_reg_read_ioctl register_acpi_notifier pci_bus_read_config_dword intel_freq_opcode dma_buf_export register_reboot_notifier intel_fbc_flush drm_mode_create_scaling_mode_property drm_atomic_helper_connector_destroy_state pci_bus_read_config_word usleep_range i915_gem_obj_to_ggtt_view chv_phy_powergate_lanes __tracepoint_i915_ppgtt_release drm_clflush_pages __tracepoint_i915_gem_request_complete __i915_wait_request dma_buf_map_attachment ioremap_nocache i915_gem_shrink drm_atomic_set_crtc_for_plane gen5_enable_gt_irq vlv_punit_read intel_display_print_error_state drm_atomic_helper_wait_for_vblanks i915_gem_cleanup_ringbuffer intel_uncore_forcewake_get__locked intel_gtt_get gen6_rps_busy drm_mode_hsync intel_cpu_fifo_underrun_irq_handler intel_trans_dp_port_sel i915_gem_throttle_ioctl intel_check_page_flip ironlake_disable_display_irq intel_has_pending_fb_unpin intel_ring_initialized i915_gem_release_all_mmaps __free_pages gen6_rps_reset_ei drm_gem_mmap i915_gem_obj_lookup_or_create_ggtt_vma __crc_i915_read_mch_val drm_mode_create sandybridge_pcode_write pv_irq_ops kmem_cache_alloc __tracepoint_i915_va_alloc intel_dp_encoder_destroy intel_ddi_set_vc_payload_alloc intel_psr_enable drm_property_create_enum drm_dp_find_vcpi_slots broxton_ddi_phy_init drm_ioctl drm_plane_cleanup intel_dp_set_m_n drm_mode_set_crtcinfo intel_panel_disable_backlight drm_framebuffer_remove i2c_del_adapter drm_atomic_helper_plane_set_property capable i915_gem_stolen_insert_node find_vma i915_gem_evict_something i915_guc_submission_init init_workarounds_ring intel_display_port_power_domain intel_runtime_pm_put intel_ring_stopped i915_vma_unbind drm_gem_prime_fd_to_handle i915_gem_busy_ioctl pm_qos_update_requirement i915_error_state_get sysfs_create_link drm_atomic_get_crtc_state intel_gmbus_get_adapter intel_edp_drrs_enable gen6_sanitize_rps_pm_mask intel_plane_obj_offset hsw_disable_pc8 intel_dsi_reset_clocks i915_gem_init_global_gtt intel_audio_codec_enable work_busy intel_setup_overlay sg_alloc_table __tracepoint_i915_pipe_update_end i915_gem_object_wait_rendering __crc_i915_gpu_busy idr2_destroy intel_power_domains_init_hw drm_gem_object_free i915_restore_state intel_dp_set_link_params per_cpu__this_cpu_off drm_crtc_get_hv_timing i915_driver_load acpi_get_handle intel_ring_reserved_space_end register_ftrace_event intel_ring_alloc_request_extras valleyview_disable_display_irqs unregister_reboot_notifier intel_connector_alloc intel_guc_suspend do_mmap_pgoff i915_gem_dumb_create drm_debug i915_gem_reset trace_profile_buf i915_cmd_parser_init_ring intel_parse_bios acpi_video_unregister synchronize_irq intel_plane_destroy mark_page_accessed intel_overlay_reset skl_plane_ctl_tiling drm_modeset_lock drm_gem_vm_close drm_dp_mst_dump_topology drm_modeset_unlock i915_driver_lastclose __symbol_get kobject_uevent_env i915_destroy_error_state drm_mode_connector_update_edid_property drm_gem_vm_open drm_fb_helper_prepare async_schedule i915_gem_object_unpin_from_display_plane idr2_find_slowpath i915_gem_request_alloc i915_gpu_lower i915_gem_check_wedge unregister_oom_notifier __crc_i915_gpu_lower intel_display_set_init_power intel_fbdev_output_poll_changed i915_gem_object_pin_fence intel_crtc_wait_for_pending_flips ironlake_check_encoder_dotclock flush_workqueue intel_guc_ucode_load drm_kms_helper_poll_enable intel_connector_atomic_get_property drm_connector_init i915_gem_get_aperture_ioctl drm_err assert_csr_loaded i915_gem_set_tiling intel_display_resume release_pages intel_ddi_pll_init skl_wm_get_hw_state drm_debugfs_create_files intel_csr_load_status_set intel_init_pipe_control intel_reset_gt_powersave intel_fb_obj_invalidate sysfs_unmerge_group i915_reset down_write __mod_pci_device_table logical_ring_flush_all_caches drm_fb_helper_add_one_connector up_write i915_driver_preclose i915_gem_init_swizzling mipi_dsi_generic_write vlv_dpio_write request_firmware_nowait __tracepoint_i915_context_free drm_atomic_set_fb_for_plane i915_gem_init intel_irq_init trace_current_buffer_lock_reserve dma_buf_unmap_attachment drm_fb_helper_release_fbi intel_backlight_unregister __create_workqueue_key __tracepoint_i915_page_directory_entry_alloc intel_is_dual_link_lvds i915_gem_release_mmap i915_gem_object_pin sysfs_remove_link intel_dp_compute_config intel_pipe_update_start kstrtoint i915_gem_obj_is_pinned simple_attr_release i915_gem_batch_pool_init i915_gem_free_object drm_dp_aux_unregister pid_task i915_gem_object_init intel_modeset_init_hw __tracepoint_i915_gem_request_add i915_gpu_idle drm_property_add_enum i915_audio_component_cleanup drm_add_edid_modes gen9_null_state trace_define_common_fields mod_timer __tracepoint_i915_flip_complete _spin_unlock_irqrestore noop_llseek i915_mch_val interval_tree_iter_next drm_read sysfs_merge_group drm_modeset_legacy_acquire_ctx intel_disable_gt_powersave drm_framebuffer_unreference __tracepoint_i915_flip_request intel_prepare_reset hsw_enable_pc8 i915_gem_execbuffer2 intel_suspend_gt_powersave intel_dp_pack_aux drm_gem_object_release list_del __tracepoint_i915_page_table_entry_alloc ibx_display_interrupt_update __sg_page_iter_next drm_dp_mst_topology_mgr_suspend destroy_workqueue intel_uncore_early_sanitize drm_probe_ddc vga_client_register drm_select_eld per_cpu__kernel_stack mutex_lock gen6_disable_rps_interrupts pci_bus_write_config_dword warn_slowpath_null ironlake_get_lanes_required intel_gpu_freq drm_send_vblank_event __tracepoint_i915_gem_shrink swiotlb_nr_tbl io_schedule kmem_cache_free ironlake_set_drps intel_dp_hpd_pulse intel_iommu_gfx_mapped debugfs_remove vbt_panel_init drm_panel_attach i915_gem_render_state_fini intel_display_power_get i915_gem_mmap_gtt i915_gem_set_caching_ioctl i915_gem_context_reset intel_modeset_init seq_putc i915_gem_suspend intel_edp_backlight_off mcount i915_ioctls intel_cleanup_ring_buffer intel_backlight_register intel_panel_enable_backlight intel_dp_mst_encoder_cleanup vlv_gps_core_read strncpy copy_to_user intel_psr_disable _cond_resched drm_atomic_state_init intel_gpu_ips_init intel_uncore_forcewake_put __tracepoint_i915_gem_evict_vm vlv_flisdsi_read drm_plane_from_index shmem_read_mapping_page_gfp drm_fb_helper_fill_var dma_buf_put param_set_bool intel_no_fbc_reason_str valleyview_enable_display_irqs intel_dp_stop_link_train assert_forcewakes_inactive drm_atomic_state_free drm_crtc_vblank_on find_next_zero_bit drm_dp_get_adjust_request_voltage sil164_ops drm_mode_create_rotation_property intel_fbc_init drm_dp_link_train_clock_recovery_delay pci_map_rom intel_gtt_chipset_flush i915_gem_retire_requests_ring i915_vma_bind acpi_lid_notifier_unregister i915_gem_l3_remap vmap drm_gem_dumb_destroy drm_mm_reserve_node drm_dp_mst_reset_vcpi_slots drm_gem_handle_create mmu_notifier_unregister skl_plane_ctl_format i915_gem_shrink_all intel_mark_busy async_synchronize_full intel_ddi_get_encoder_port i915_gem_mmap_gtt_ioctl i915_mutex_lock_interruptible i915_gem_wait_ioctl intel_logical_ring_reserve_space unregister_acpi_notifier drm_rect_rotate_inv intel_display_suspend drm_put_dev i915_gem_userptr_ioctl vlv_power_sequencer_reset drm_crtc_init_with_planes drm_has_preferred_mode intel_register_dsm_handler drm_mode_create_tv_properties i915_gem_obj_size drm_mode_duplicate _spin_lock_irq i915_gem_evict_vm drm_atomic_helper_prepare_planes sscanf drm_object_attach_property printk intel_edp_panel_on __memcpy_toio drm_helper_mode_fill_fb_struct __mutex_init vlv_wm_get_hw_state drm_crtc_vblank_put __crc_i915_gpu_raise mutex_lock_interruptible gen6_disable_pm_irq i915_gem_context_getparam_ioctl jiffies_to_msecs drm_mode_set_name intel_psr_init intel_lrc_irq_handler i915_gem_load intel_fb_align_height drm_clflush_sg dev_err intel_enable_rc6 intel_display_port_aux_power_domain intel_crtc_destroy_state hweight8 pci_iounmap i915_guc_submission_fini i915_gem_object_put_pages intel_uncore_forcewake_domain_to_str _ctype intel_panel_destroy_backlight drm_plane_index intel_crtc_duplicate_state intel_psr_single_frame_update i915_gem_clflush_object acpi_lid_open i915_parse_cmds intel_edp_panel_vdd_on drm_atomic_commit default_llseek drm_noop i915_gem_get_gtt_size i915_gem_restore_fences pci_set_dma_mask drm_mode_copy drm_dp_link_rate_to_bw_code drm_mode_connector_set_path_property i915_redisable_vga remove_conflicting_framebuffers drm_fb_helper_cfb_copyarea intel_logical_ring_stop drm_atomic_state_alloc i915_cmd_parser_get_version drm_irq_install drm_mode_connector_attach_encoder ida2_simple_get intel_overlay_attrs intel_cleanup_overlay memset intel_overlay_print_error_state dmi_check_system acpi_is_video_device __tracepoint_i915_gem_ring_flush drm_mm_init trace_define_field intel_opregion_setup intel_ddi_set_pipe_settings i915_firmware_load_error_print del_timer_sync i915_gem_object_set_cache_level pci_get_bus_and_slot drm_fb_helper_set_suspend intel_panel_fini i915_gem_pread_ioctl intel_ddi_prepare_link_retrain i915_gem_obj_to_vma pgprot_writecombine chv_phy_powergate_ch ns2501_ops round_jiffies_up_relative intel_uncore_sanitize drm_dp_check_act_status intel_release_load_detect_pipe drm_dp_mst_deallocate_vcpi __bitmap_or i915_gem_init_stolen hweight16 pci_set_master vga_switcheroo_unregister_client intel_gmch_panel_fitting drm_handle_vblank intel_overlay_capture_error_state intel_gpu_ips_teardown drm_atomic_helper_set_config drm_rect_debug_print intel_dp_rate_select per_cpu__cpu_number drm_atomic_helper_update_legacy_modeset_state drm_fb_helper_pan_display __init_waitqueue_head intel_attach_broadcast_rgb_property intel_sbi_write skl_ddb_get_hw_state i915_gpu_busy i915_gem_render_state_init intel_vgt_balloon i915_ppgtt_create __drm_atomic_helper_crtc_duplicate_state i915_redisable_vga_power_on bxt_find_best_dpll drm_atomic_helper_connector_duplicate_state intel_create_plane_state i915_gem_find_active_request intel_modeset_vga_set_state drm_atomic_set_mode_for_crtc i915_gem_mmap_ioctl intel_ring_cacheline_align intel_pipe_has_type idr2_remove drm_fb_helper_unregister_fbi intel_init_clock_gating i915_gem_object_get_pages intel_opregion_fini kasprintf intel_vgt_deballoon simple_attr_read drm_vblank_count i915_wait_request i915_gem_object_ggtt_unpin_view __drm_atomic_helper_plane_duplicate_state intel_set_memory_cxsr intel_enable_gt_powersave down_read strcmp intel_mode_from_pipe_config pci_mem_start __mmdrop mutex_trylock gen6_enable_rps_interrupts intel_guc_fw_status_repr i2c_add_adapter intel_dsi_init intel_csr_load_program drm_connector_cleanup intel_hdmi_init_connector __list_add jiffies vlv_punit_write intel_panel_detect drm_dp_channel_eq_ok vga_put drm_pci_set_busid intel_atomic_state_alloc set_page_dirty i915_suspend_switcheroo intel_update_watermarks drm_mm_init_scan drm_dp_mst_allocate_vcpi drm_universal_plane_init acpi_video_register drm_detect_monitor_audio drm_av_sync_delay i915_gem_pwrite_ioctl intel_pch_fifo_underrun_irq_handler trace_nowake_buffer_unlock_commit i915_gem_object_put_fence gen6_reset_rps_interrupts __i915_add_request seq_read __drm_atomic_helper_crtc_destroy_state intel_crtc_active __tracepoint_i915_gem_request_retire intel_edp_drrs_invalidate __intel_display_power_is_enabled intel_suspend_hw ilk_wm_get_hw_state intel_execlists_retire_requests shmem_truncate_range filter_current_check_discard _spin_lock_irqsave tsc_khz pci_bus_alloc_resource hsw_dp_set_ddi_pll_sel debugfs_create_file drm_object_property_set_value drm_pci_free drm_modeset_acquire_fini drm_dp_mst_hpd_irq drm_encoder_init intel_uncore_forcewake_reset i915_max_ioctl param_set_int i915_gem_object_attach_phys pci_bus_write_config_word drm_vblank_init intel_execlists_ctx_id intel_irq_install drm_dp_mst_topology_mgr_destroy drm_panel_init __tracepoint_i915_gem_object_create gen8_null_state intel_gmbus_set_speed i915_gem_madvise_ioctl hweight32 gen6_null_state bitmap_set mutex_unlock intel_ring_reserved_space_use cancel_delayed_work_sync intel_logical_ring_alloc_request_extras drm_mm_insert_node_in_range_generic vlv_nc_read intel_lvds_init drm_kms_helper_hotplug_event i915_gem_vma_destroy ring_buffer_event_data init_timer_key intel_panel_init try_acquire_console_sem i915_gem_set_seqno hdmi_infoframe_pack intel_dp_init perf_swevent_get_recursion_context __const_udelay pm_qos_add_requirement sandybridge_pcode_read i915_ppgtt_init_ring drm_vblank_cleanup __get_user_pages_fast drm_gem_free_mmap_offset assert_pipe intel_uncore_forcewake_put__locked sg_pcopy_from_buffer list_sort acpi_evaluate_object intel_plane_helper_funcs sg_next i915_check_and_clear_faults drm_dp_calc_pbn_mode i915_gem_object_get_fence i915_gem_sw_finish_ioctl kmemdup __sg_page_iter_start intel_dp_mst_encoder_init i915_gem_stolen_insert_node_in_range vlv_bunit_read seq_write queue_work pci_get_class intel_enable_dsi_pll intel_queue_rps_boost_for_request assert_pll intel_hpd_cancel_work intel_logical_ring_begin ktime_get __mmu_notifier_register sysfs_create_files perf_tp_event_regs cancel_work_sync drm_crtc_vblank_off i915_gem_object_unpin_fence intel_fini_pipe_control seq_printf drm_helper_probe_single_connector_modes skl_uninit_cdclk schedule_timeout_killable intel_unpin_ringbuffer_obj drm_dp_mst_topology_mgr_set_mst intel_unregister_dsm_handler intel_dp_is_edp acpi_bus_get_device find_next_bit drm_modeset_backoff schedule_work i915_gem_object_sync _spin_lock intel_ring_reserved_space_reserve intel_engine_create_ringbuffer i915_gem_gtt_init drm_rect_calc_hscale_relaxed backlight_device_register intel_modeset_preclose intel_set_rps intel_plane_atomic_calc_changes usecs_to_jiffies drm_rect_calc_vscale_relaxed i915_gpu_turbo_disable vga_switcheroo_process_delayed_switch intel_detect_pch intel_ring_get_active_head intel_enable_gtt intel_dp_add_properties perf_swevent_put_recursion_context __tracepoint_i915_gem_request_wait_end drm_mm_scan_add_block i915_get_extra_instdone intel_ddi_get_crtc_new_encoder i915_gem_restore_gtt_mappings drm_atomic_get_plane_state __tracepoint_i915_pipe_update_vblank_evaded i2c_transfer drm_dp_mst_topology_mgr_resume i915_global_gtt_cleanup drm_atomic_helper_swap_state intel_opregion_notify_encoder intel_dvo_init i915_queue_hangcheck drm_property_create_range intel_dp_mst_resume i915_gem_stolen_remove_node i915_gem_execbuffer_retire_commands arch_phys_wc_add i915_gem_obj_bound broxton_ddi_phy_uninit pci_disable_device dma_buf_detach mchdev_lock intel_hdmi_init mipi_dsi_dcs_write_buffer boot_cpu_data seq_puts hsw_disable_ips malloc_sizes drm_match_cea_mode intel_edp_drrs_flush i915_gem_open drm_mode_destroy vlv_force_pll_on single_release interval_tree_insert i915_disable_pipestat intel_overlay_switch_off i915_error_state_put intel_i2c_reset sg_copy_from_buffer i915_gem_retire_requests __copy_user_nocache __tracepoint_i915_gem_object_clflush cpufreq_cpu_get drm_atomic_state_clear sg_nents vlv_flisdsi_write intel_lr_context_unpin intel_psr_invalidate drm_pci_exit autoremove_wake_function i915_gem_obj_ggtt_offset_view intel_ddi_init_dp_buf_reg __tracepoint_i915_gem_object_fault drm_mode_config_reset intel_get_pipe_from_crtc_id intel_gpu_reset devm_kzalloc i915_gem_get_gtt_alignment intel_fbdev_restore_mode memset_io skl_init_cdclk i915_gem_execbuffer_move_to_active i915_gem_object_create_from_data __tracepoint_i915_ppgtt_create vga_get drm_modeset_drop_locks gen6_rps_boost component_add i915_ppgtt_init drm_mode_config_cleanup drm_gem_dmabuf_release ddi_signal_levels pci_unmap_rom __tracepoint_i915_gem_request_wait_begin intel_fbdev_fini __tracepoint_i915_gem_ring_sync_to i915_gem_alloc_context_obj hsw_enable_ips i915_compat_ioctl bxt_disable_dc9 assert_fdi_rx_pll intel_hpd_init_work release_resource acpi_evaluate_integer schedule_timeout_uninterruptible ida2_init intel_gmch_probe __tracepoint_i915_gem_object_pwrite drm_wait_one_vblank strlen iomem_resource drm_edid_to_eld i915_teardown_sysfs intel_ddi_get_config __tracepoint_intel_gpu_freq_change i915_gem_object_set_to_gtt_domain drm_hdmi_vendor_infoframe_from_display_mode assert_shared_dpll drm_connector_index idr2_for_each i915_ggtt_view_rotated i915_guc_submission_enable intel_prepare_ddi param_get_int intel_rcs_context_init_mocs intel_init_bsd_ring_buffer kvfree intel_gmbus_is_valid_pin intel_hpd_irq_handler intel_fbc_cleanup_cfb drm_fb_helper_initial_config single_open intel_fbdev_initial_config intel_plane_destroy_state drm_framebuffer_reference gen7_null_state drm_calc_vbltimestamp_from_scanoutpos ioremap_wc intel_power_domains_fini drm_fb_helper_cfb_fillrect skl_max_scale intel_has_gpu_reset trace_profile_buf_nmi intel_finish_page_flip intel_crtc_restore_mode __tracepoint_i915_vma_bind intel_crtc_to_shared_dpll drm_rect_calc_vscale drm_crtc_index intel_tv_init i915_gem_obj_ggtt_bound_view intel_create_rotation_property intel_fb_stride_alignment sysfs_remove_bin_file drm_atomic_helper_update_plane drm_get_edid simple_read_from_buffer drm_calc_timestamping_constants drm_dp_dpcd_write i915_gem_context_get vlv_gpio_nc_read up_read intel_cleanup_gt_powersave intel_dp_max_link_rate intel_execlists_submission intel_fbdev_init intel_fbc_invalidate drm_get_connector_status_name drm_compat_ioctl intel_csr_ucode_init put_pid intel_pipe_to_cpu_transcoder pnp_range_reserved __intel_framebuffer_create vlv_wait_port_ready i915_debugfs_cleanup interval_tree_remove intel_init_audio intel_runtime_pm_enable_interrupts kref_put drm_dp_update_payload_part1 __tracepoint_i915_page_directory_pointer_entry_alloc intel_display_power_is_enabled msleep i915_gem_object_create_stolen_for_preallocated get_seconds intel_ringbuffer_free i915_gem_context_init chv_calc_dpll_params __tracepoint_i915_gem_object_destroy __kmalloc vlv_ccu_read intel_gtt_clear_range i915_gem_context_open pci_bus_read_config_byte sg_pcopy_to_buffer intel_ring_flush_all_caches local_clock per_cpu__current_task device_remove_bin_file tracepoint_probe_register intel_find_panel_downclock drm_fb_helper_set_par drm_atomic_get_connector_state drm_prime_gem_destroy __tracepoint_i915_gem_object_change_domain drm_release i915_gem_object_pin_to_display_plane kmem_cache_destroy intel_dp_init_connector __crc_i915_gpu_turbo_disable intel_runtime_pm_enable system_wq i915_ppgtt_release alloc_pages_current flush_work intel_dp_sink_dpms drm_helper_move_panel_connectors_to_head vgacon_text_force intel_setup_gmbus intel_power_domains_init i915.ko.debug .rodata.str1.1 .rodata.str1.8 .rela.data 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