ELF > h6 @ @ GNU ?n+NƵ j: UH 12 F F ffffff. UH H f UHHPH]LeLm @uHGIԉHuIfE fE fUHUHU fE LefMfEH? uG u1H]LeLmÉH 11 HcI9w.H 1 ÉH H 1 A4H 1 @ UHSH H HUH xEU Љ1H[f UHSH H HUH xEU f1H[UHSH H HUHl Ex(UE Ef3
u 1H[H 1f ffff. UHSH H HUH x EU U 1H[ffff. UHSH H HU H Ox95 u6Et t Et t 1Et H[MUH u1 ffffff. UHH`H]LeLmLuL} D eH%( HE1HA HAIIHH)Lt$IE I~LLE.A HCH;Hu fE LufD}fE 1u&HUeH3%( u(H]LeLmLuL}Ð= u H H 1 ݃H 1 1HcI9wH 1 5A4H 1U U UHH H]LeLm Ѐ IH5 I HHtmH LhL ~ H3xIHCH ^ HHH t5 H 1 H 1H]LeLmf D IZarlink IZL10313 LSLH@DVB-f@S Hǃ H ƃ H]LeLm IZarlink IMT312 DVLcLX@B-S Hǃ ƃ H]LeLm D IVP310 DVHZarlink HSLh@B-S Hǃ ƃ H]LeLmffff. UHATSH H 1E A tGEu2࿈EHU H߈EH[A\f. @E HU HZxEffff. UHH H w9E E@E D5 HO@A EHUE UHH`H]LeLmLuL} H LeI LH Eτ L Hs } HUι g HEg Lu { HL& Lt HD}x{
UE L HxLEE E E E E E E E DAE 1H]LeLmLuL} HUι g HEnxHU { H4x5 UE0H 1i = AEYA H 1DAD = H A 1EH HcH
HH4 1L) UHATSH H LeELH\xK tOHU Hx(EL H߃E1NH[A\ @ L HE xֹ LT HE
sUHH H]Le L vH]Lef D HU LRxEEE HUL @
D E@1H]LeNffff. UHH H]Le L vH]Lef D HU LxEEEHUL @
D E1H]LeNffff. UHH0H]LeLm VL HvH]LeLmf D HU߹ LxKHھ L
xESLm L@ LExd 1nEL L@E1NAffff. UHAUATSH( eH%( HE1H LeL※ HE+s L HEπ H HUй V HEEEEEE E E
Lm C" Hߍ QrUH ULT L1 HE23x ESS L` H߈ExM L3 HEEx,L 9 HEi1Nf. HUeH3%( H([A\A]f L HEπwxù LT HEEVx LT HE 9x LU HE k_ E33 D UHH`H]LeLm eH%( HE1HL = I A$; s)HUeH3%( H]LeLm ; wA|$wAD$; r; wAD$ wttA <tC<t?<uHU LqA|$5 A
H0 HtLHH` Ht1HAD$1ҹ = E E@EE EEEE?EEE E?E?E@EAD$f?UAT$ D
DA|$ EwEDHU LE.HU LE@ 1i H H 9Aƅ HV-A Aƅ H+ A 5 A A > e A F B , B B , # 6 B J A A A - M ] B z A A P [ B A =
F B R @ Y ` ? g B s . z B , B # B A G ? ( _ h f B n > | A A A R " ? X W B ~ B q B A
A a A A I A S
E w @ A l @ u | B Zarlink ???? DVB-S ~ p N
@ mt312_write mt312_read mt312_set_frontend debug 0 p p @ ( 8 P @
H ` p <7>%s: ret == %d
<7>mt312: R(%d): %02x
<7>mt312: W(%d): <7>mt312: %s: ret == %d
<7>mt312: sr(auto) = %u
<7>mt312: *sr(manual) = %lu
<7>mt312: %s: Freq %d
<7>mt312: agc=%08x err_db=%hd
<7>mt312: QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x, FEC_STATUS: 0x%02x
<4>Only Zarlink VP310/MT312/ZL10313 are supported chips.
<7>mt312: sym_rat_op=%d dec_ratio=%d
license=GPL author=Matthias Schwarzott author=Andreas Oberritter description=Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver parm=debug:Turn on/off frontend debugging (default:off). parmtype=debug:int srcversion=A1BC9EF06B80DB286CEA8CF depends=i2c-core vermagic=2.6.32-696.20.1.el6.x86_64 SMP mod_unload modversions # C H D
< mt312_attach D E D u D D D ( D *0 D 8 D @ D H D P D X D Y ` D h D , p D x D D E D > D
@#R module_layout msleep i param_get_int ˑ malloc_sizes ? i2c_transfer __const_udelay %K param_set_int cs printk 9 mcount __stack_chk_fail D kmem_cache_alloc_trace z kfree dl# memcpy mt312 ` d module.sig ^ Zkk
Bh)hG 1 _pAYo-9$˹
9 X.aGRWfӧR
! ! 0 / P : @ O @ G c P r p S p I p Y p i
' P 8 N [ R n } - ` , A 9 @ ( #
3
J V ` ` # s @ @ 0 { y / < I W mt312.c mt312_get_tune_settings mt312_release mt312_read debug __func__.25783 mt312_read_ucblocks mt312_read_snr mt312_read_signal_strength mt312_read_ber mt312_read_status mt312_write __func__.25821 mt312_ops mt312_i2c_gate_ctrl mt312_set_voltage mt312_get_frontend mt312_sleep mt312_set_tone mt312_send_burst mt312_send_master_cmd mt312_initfe mt312_set_frontend __func__.26325 __mod_license839 __mod_author838 __mod_author837 __mod_description836 __mod_debug834 __mod_debugtype833 __param_debug __param_str_debug __ksymtab_mt312_attach __kstrtab_mt312_attach __kcrctab_mt312_attach mt312.mod.c _rheldata __mod_srcversion37 __module_depends ____versions __mod_vermagic5 __this_module __crc_mt312_attach memcpy kfree kmem_cache_alloc_trace __stack_chk_fail mcount printk param_set_int mt312_attach __const_udelay i2c_transfer malloc_sizes param_get_int msleep mt312.ko.debug (E .rodata.str1.1 .rodata.str1.8 .data .rheldata .rela.rodata .rela__kcrctab .symtab .rela__ksymtab .strtab .shstrtab .rela__mcount_loc .note.gnu.build-id .gnu.linkonce.this_module .note.module.sig .gnu_debuglink .rela__param .modinfo __ksymtab_strings __versions .bss .rela.text @ $ p H 4 @ ) / p 2 2 ! ( ! ` X " S " 0 A P" < X"
p"
y " t # % $ % @ @( @( 0 p* p* x K * ; b 1 ^ 85 j L5