ELF > h @ @ GNU g=諕xZA UHATS H It7H I$ I$ 1 [A\f. H( Ht勗h t81f D I$( HcH4Ht
I$0 A9$h wI$0 I$( [A\ UHATS H H L#u * IH HL I I$uH H L#u#IH HL I I$uH H L#u
+ IH HL I I$uH= [A\fff. UHH H]LeLm
LH Hu5HID$ AHID$E H]LeD LmH 1 fffff. UH H t]vc@H tO H t:L @ H t% H t 0 H uO f D H tvzH t H t̃H t H 1 1f D H t H t0H u @ H `vNH NH u
H (H H HG @ H H 9 H H
H H fffff. UHHLd$A5 H $HuuD ǃ ǃ Hǃ fǃ$ fǃ& ǃ ǃ ǃ ǃ ǃ Ld$H $1sH H1 nffff. UHH H]LeLmLuL} H HtGH HHH tFHHHHH ; s-H]LeLmLuL}H 1 H 룋
AH= 1E11IH4 HI9LGH9HBHIH9uH{LuL01IHI6 HIHIT5 HHHu܅HE HxtCAL
1L I49L1 H;0 H
uHL9uH 1( LH 1 5 H 1 (L1H HH1 HH 1 LH 1 1L0$L1I H 1 HA t5DAAtӉIT H0HH9w뾐HcHDՀH 1 H E11IWfffff. UH `tEvK
t6vd t' t tH 1 1 f D
tv?0 tPtރu D qtɁ tpuf D tuf UHAVAUATSH D I 1IE1E1 E E$$ IcH H)IcH pthEt[H LcHL1H)J IH I)f D 3t E uHHD9|ADːAI A
NA E fA$$ D
E fADŽ$$ 1LH[A\A]A^f E$$ IcH H)IcHЋ A3$ Y D E H[A\A]A^HcH HH)H I$ A$$ fA$& A$& I$ fADŽ$$ A$ |A$ D E 1H[A\A]A^Ë= A$$ A$ ЃA fA$$ H[A\A]A^A$$ fA$& L= A$ L AcA$ HEHMHH 1 1*H 1 2A$ H H1 H 1 PH 1 Jf UH D Eu H 1 @ UHSHX H H]eH%( HE1H H HUeH3%( uHX[ f D UHATS HH AH A<; wLH8 Hc D D; D t[A\f tDH 1 H 1 H A+4H H1 ̐UHAVAUATSH L Ll
IHI I LL)HHwwM9LJP v)d @ P IHcʃM9H P r=LL HuͺP LL Ht'HHE HEf D 1H[A\A]A^I> P LL HuP ~*IE1 I AI D;P |fff. UHAWAVAUATSH( HUIILHIMHcЅHU eH% eL4% LHHǀHAF AN LLHuLLE HEAfLEeH% LHP ~&IE1 I AI D;P |HEH([A\A]A^A_HuLLLLE LEHEUHAWAVAUATSH( HUIILHIMHcЅHU eH% eL4% LHHǀHAF AN LLHuLLE HEAfLEeH% LHP ~&IE1 I AI D;P |HEH([A\A]A^A_HuLLLLE LEHEUHH0H]LeLmLu H= AuH]LeLmLuÐ =? w= v 15 tA @ E1AA DmA 1DAu܉։ AHH8 @08H H D4 D0 1 A ( E ^ 8 h t { 4 h & 8 ~ 4 h
0
B u ~ 2 R B i r
3 m t L P P 2 4 4 p 4 8 ) < 4 9 @ < K j q < w @ @ 4 N 4 j q 4 8 < < f 4 | 8 4 < C - , 3 0 E 0 s 4 4 8
4 " 8 7
> V 8 ] 4 h 4 | 4 5 4 H O [ b H @
F
\ k r ~ P X p
$ 9 @ O V e l X ( 5 < H ` O d i { 4 c 4 * 4 c P j 4 ! 4 ! ! S" H Z" n" s" y" 3 " X " " " " H " " # # %# <# # # r$ 4 $ 8 $ $ $ $ $ $ $
% % (% 5% D% T% 4 f% m% {% 4 % @ % % !& 3 |& 3 & 3 & & & & ' #' R' 3 b' P i' ' ' ' x ' ' ' ' X ' ' ) 0 $) ) 4 ) 3 * 4 #+ 7 x+ 3 N, U, a, h, , , , ( , , , , , , , - ( - - - 2- 9- f- p m- - 8 - UHATS H 1HH L I$8 L H= I<$I( uH= [A\ , 4 ; @ P \ a f UHAWAVAUATSH85 t tH 1A H5 Ѐ HH uH A u L H LH A$ I$ ID$P ID$ ID$X ID$ ID$( ID$0 ID$ ADŽ$ = u = t ǃ
ǃ ǃ @
= uǃ A$ H HǀP H H L}HEH}1LD7 Au A0tH 1A
H}A ?:uH1LH} AHEȀ8,uHHEH5 Ѐ H DhDpHH H HEȀ8 JH H L}HEH}1LD7 Au A0tH 1A !
H}A ?:uH1LH} AHEȀ8,uHHEH5 Ѐ H DhDpHH H HEȀ8 JH H L}HEH}1LD7 Au A0tH 1A S H}A ?:uH1LH} AHEȀ8,uHHEH5 Ѐ HuH A DhDpHH H HEȀ8 7H= At 1H EDO
toH rHHHHH9tH 1 HBI$ H
QDA$ HA$ A$ = H tIHH@1ҾЀ H H< HH uH A H HH L I$@ tH 1 LJ 1҃A$ LPM$@ pA$L DHAE$P D@A1A$` LIDE$H A$h HLI$X ADA$p ADA$x DADŽ$ A$t 1A$l A F E$d uADŽ$ K ub " EA$ ) uADŽ$ H 1 x A$ tBI$@ wADŽ$| ADŽ$ ZADŽ$| ADŽ$ @I$@ wADŽ$| ADŽ$ ADŽ$| ADŽ$ = I$@ MH 1E1lE$H L.HI9wMuH 1A i DHUHMHuA IHMMnINHULHuI(L) A9rHA$ tb vH 1A DHUHM HIcHk(J4 HMIHHHUHPA$ 1# ;
u u A$ HcHk0H uA$ uH 1 I$@ H 1H A$L H 1 A$P H 1 A$H H 1
A$h H 1 A$l H 1 A$ H 1 A$p H 1 A$t H 1 A$x H 1 I$X H 1H
A$| H 1 A$ H 1 A$ H 1 H= H B H= IvA H@ HtHx u Hx uH 1A I Hx u Hx( uH 1A " A$h HI$ uH A A$` HI$ u$H A I$ I$ A$h 1M$ H A$h H 1HI$( u'H I$( HcʃH A;$h rA$` E111H HI$0 u H 1L gA$` HHI$8 u A$` H 1A 'A$` HH L% Hu L LmHEH}1LD7 uA0tH LI$ H tH 1 HEȀ8,uHHEHEȀ8 uH= Au H= H AtJH8 E1 H H= H;AH( A uH= H8D[A\A]A^A_AAA $ 1 = L V _ j ' % 0 0# % = I U a m $ / J , Q 0 V j p < @ $ 8 Z n { @ L P # 3 8 O Z u | L D 8 " B x I $ { = e ( r | | 4 : B ( _ t X {
1 G + V 2 A o H W ^ m x
9
F
X
l
8 w
J O c h w P , : E L r w cache_file overridesize rptwear gravepages bitflips weakpages weakblocks badblocks parts dbg log do_delays bus_width input_cycle output_cycle erase_delay programm_delay access_delay fourth_id_byte third_id_byte second_id_byte first_id_byte h p x <7>[nandsim] debug: read_word
<3>[nandsim] error: get_state_name: unknown state, BUG
<7>[nandsim] debug: switch_to_ready_state: switch to %s state
<3>[nandsim] error: Erase counter total overflow
<3>[nandsim] error: Erase counter overflow for erase block %u
<6>[nandsim] *** Wear Report ***
<6>[nandsim] Total numbers of erases: %lu
<6>[nandsim] Number of erase blocks: %u
<6>[nandsim] Average number of erases: %lu
<6>[nandsim] Maximum number of erases: %lu
<6>[nandsim] Minimum number of erases: %lu
<6>[nandsim] Number of ebs with erase counts from %lu to %lu : %lu
<6>[nandsim] *** End of Wear Report ***
<3>[nandsim] error: get_state_by_command: unknown command, BUG
<7>[nandsim] debug: find_operation: operation found, index: %d, state: %s, nxstate %s
<7>[nandsim] debug: find_operation: no operation found, try again with state %s
<7>[nandsim] debug: find_operation: no operations found
<7>[nandsim] debug: find_operation: BUG, operation must be known if address is input
<7>[nandsim] debug: find_operation: there is still ambiguity
<7>[nandsim] debug: device_ready
<3>[nandsim] error: wrong bus width (%d), use only 8 or 16
<3>[nandsim] error: unable to allocate core structures.
<3>[nandsim] error: invalid weakblocks.
<3>[nandsim] error: unable to allocate memory.
<3>[nandsim] error: invalid weakpagess.
<3>[nandsim] error: invalid gravepagess.
<3>[nandsim] error: can't register NAND Simulator
<3>[nandsim] error: overridesize is too big
<3>[nandsim] error: Too many erase blocks for wear reporting
<3>[nandsim] error: init_nandsim: nandsim is already initialized
<3>[nandsim] error: init_nandsim: unknown page size %u
<3>[nandsim] error: too many partitions.
<3>[nandsim] error: bad partition size.
<4>[nandsim] warning: 16-bit flashes support wasn't tested
flash size with OOB: %llu KiB
<3>[nandsim] error: alloc_device: cache file not readable
<3>[nandsim] error: alloc_device: cache file not writeable
<3>[nandsim] error: alloc_device: unable to allocate pages written array
<3>[nandsim] error: alloc_device: unable to allocate file buf
<3>[nandsim] error: alloc_device: unable to allocate page array
<3>[nandsim] error: cache_create: unable to create kmem_cache
<3>[nandsim] error: init_nandsim: unable to allocate %u bytes for the internal buffer
<3>[nandsim] error: invalid badblocks.
<3>[nandsim] error: write_buf: data input isn't expected, state is %s, switch to STATE_READY
<3>[nandsim] error: write_buf: too many input bytes
<7>[nandsim] debug: write_buf: %d bytes were written
<4>[nandsim] warning: read_page: flipping bit %d in page %d reading from %d ecc: corrected=%u failed=%u
<4>[nandsim] warning: simulating read error in page %u
<4>[nandsim] warning: do_state_action: wrong page number (%#x)
<3>[nandsim] error: do_state_action: column number is too large
<7>[nandsim] debug: read_page: page %d not written
<7>[nandsim] debug: read_page: page %d written, reading from %d
<3>[nandsim] error: read_page: read error for page %d ret %ld
<7>[nandsim] debug: read_page: page %d not allocated
<7>[nandsim] debug: read_page: page %d allocated, reading from %d
<7>[nandsim] debug: do_state_action: (ACTION_CPY:) copy %d bytes to int buf, raw offset %d
<7>[nandsim] log: read page %d
<7>[nandsim] log: read page %d (second half)
<7>[nandsim] log: read OOB of page %d
<3>[nandsim] error: do_state_action: device is write-protected, ignore sector erase
<3>[nandsim] error: do_state_action: wrong sector address (%#x)
<7>[nandsim] debug: do_state_action: erase sector at address %#x, off = %d
<7>[nandsim] log: erase sector %u
<7>[nandsim] debug: erase_sector: freeing page %d
<4>[nandsim] warning: simulating erase failure in erase block %u
<4>[nandsim] warning: do_state_action: device is write-protected, programm
<3>[nandsim] error: do_state_action: too few bytes were input (%d instead of %d)
<7>[nandsim] debug: prog_page: writing page %d
<3>[nandsim] error: prog_page: read error for page %d ret %ld
<3>[nandsim] error: prog_page: write error for page %d ret %ld
<7>[nandsim] debug: prog_page: allocating page %d
<3>[nandsim] error: prog_page: error allocating memory for page %d
<7>[nandsim] debug: do_state_action: copy %d bytes from int buf to (%#x, %#x), raw off = %d
<7>[nandsim] log: programm page %d
<4>[nandsim] warning: simulating write failure in page %u
<7>[nandsim] debug: do_state_action: set internal offset to 0
<3>[nandsim] error: do_state_action: BUG! can't skip half of page for non-512byte page size 8x chips
<7>[nandsim] debug: do_state_action: set internal offset to %d
<7>[nandsim] debug: do_state_action: BUG! unknown action
<7>[nandsim] debug: switch_state: operation is known, switch to the next state, state: %s, nxstate: %s
<7>[nandsim] debug: switch_state: operation is unknown, try to find it
<7>[nandsim] debug: switch_state: double the column number for 16x device
<4>[nandsim] warning: switch_state: not all bytes were processed, %d left
<7>[nandsim] debug: switch_state: operation complete, switch to STATE_READY state
<7>[nandsim] debug: switch_state: the next state is data I/O, switch, state: %s, nxstate: %s
<3>[nandsim] error: switch_state: BUG! unknown data state
<3>[nandsim] error: switch_state: BUG! unknown address state
<3>[nandsim] error: read_buf: chip is disabled
<3>[nandsim] error: read_buf: ALE or CLE pin is high
<4>[nandsim] warning: read_buf: unexpected data output cycle, current state is %s
<3>[nandsim] error: read_buf: too many bytes to read
<7>[nandsim] debug: read_buf: switch to the next page (%#x)
<7>[nandsim] debug: verify_buf: the buffer is OK
<7>[nandsim] debug: verify_buf: the buffer is wrong
<3>[nandsim] error: read_byte: chip is disabled, return %#x
<3>[nandsim] error: read_byte: ALE or CLE pin is high, return %#x
<4>[nandsim] warning: read_byte: unexpected data output cycle, state is %s return %#x
<7>[nandsim] debug: read_byte: return %#x status
<4>[nandsim] warning: read_byte: no more data to output, return %#x
<7>[nandsim] debug: read_byte: read ID byte %d, total = %d
<7>[nandsim] debug: read_byte: all bytes were read
<7>[nandsim] debug: read_byte: switch to the next page (%#x)
<3>[nandsim] error: write_byte: chip is disabled, ignore write
<3>[nandsim] error: write_byte: ALE and CLE pins are high simultaneously, ignore write
<4>[nandsim] warning: write_byte: command (%#x) wasn't expected, expected state is %s, ignore previous states
<7>[nandsim] debug: command byte corresponding to %s state accepted
<7>[nandsim] debug: write_byte: operation isn't known yet, identify it
<3>[nandsim] error: write_byte: address (%#x) isn't expected, expected state is %s, switch to STATE_READY
<3>[nandsim] error: write_byte: no more address bytes expected
<7>[nandsim] debug: write_byte: address byte %#x was accepted (%d bytes input, %d expected)
<7>[nandsim] debug: address (%#x, %#x) is accepted
<3>[nandsim] error: write_byte: data input (%#x) isn't expected, state is %s, switch to %s
<4>[nandsim] warning: write_byte: %u input bytes has already been accepted, ignore write
<3>[nandsim] error: write_byte: unknown command %#x
STATE_CMD_READ1 STATE_CMD_READ0 STATE_CMD_PAGEPROG STATE_CMD_READOOB STATE_CMD_READSTART STATE_CMD_ERASE1 STATE_CMD_STATUS STATE_CMD_STATUS_M STATE_CMD_SEQIN STATE_CMD_READID STATE_CMD_ERASE2 STATE_CMD_RESET STATE_CMD_RNDOUT STATE_CMD_RNDOUTSTART STATE_ADDR_PAGE STATE_ADDR_SEC STATE_ADDR_ZERO STATE_ADDR_COLUMN STATE_DATAIN STATE_DATAOUT STATE_DATAOUT_ID STATE_DATAOUT_STATUS STATE_DATAOUT_STATUS_M STATE_READY STATE_UNKNOWN NAND simulator partition %d flash size: %llu MiB
page size: %u bytes
OOB area size: %u bytes
sector size: %u KiB
pages number: %u
pages per sector: %u
bus width: %u
bits in sector size: %u
bits in page size: %u
bits in OOB size: %u
page address bytes: %u
sector address bytes: %u
options: %#x
nandsim drivers/mtd/nand/nandsim.c <7>[nandsim] log: reset chip
& + description=The NAND flash simulator author=Artem B. Bityuckiy license=GPL parm=cache_file:File to use to cache nand pages instead of memory parm=overridesize:Specifies the NAND Flash size overriding the ID bytes. The size is specified in erase blocks and as the exponent of a power of two e.g. 5 means a size of 32 erase blocks parm=rptwear:Number of erases inbetween reporting wear, if not zero parm=gravepages:Pages that lose data [: maximum reads (defaults to 3)] separated by commas e.g. 1401:2 means page 1401 can be read only twice before failing parm=bitflips:Maximum number of random bit flips per page (zero by default) parm=weakpages:Weak pages [: maximum writes (defaults to 3)] separated by commas e.g. 1401:2 means page 1401 can be written only twice before failing parm=weakblocks:Weak erase blocks [: remaining erase cycles (defaults to 3)] separated by commas e.g. 113:2 means eb 113 can be erased only twice before failing parm=badblocks:Erase blocks that are initially marked bad, separated by commas parm=parts:Partition sizes (in erase blocks) separated by commas parm=dbg:Output debug information if not zero parm=log:Perform logging if not zero parm=do_delays:Simulate NAND delays using busy-waits if not zero parm=bus_width:Chip's bus width (8- or 16-bit) parm=input_cycle:Word input (to flash) time (nanodeconds) parm=output_cycle:Word output (from flash) time (nanodeconds) parm=erase_delay:Sector erase delay (milliseconds) parm=programm_delay:Page programm delay (microseconds parm=access_delay:Initial page access delay (microseconds) parm=fourth_id_byte:The fourth byte returned by NAND Flash 'read ID' command parm=third_id_byte:The third byte returned by NAND Flash 'read ID' command parm=second_id_byte:The second byte returned by NAND Flash 'read ID' command (chip ID) parm=first_id_byte:The first byte returned by NAND Flash 'read ID' command (manufacturer ID) parmtype=cache_file:charp parmtype=overridesize:uint parmtype=rptwear:uint parmtype=gravepages:charp parmtype=bitflips:uint parmtype=weakpages:charp parmtype=weakblocks:charp parmtype=badblocks:charp parmtype=parts:array of ulong parmtype=dbg:uint parmtype=log:uint parmtype=do_delays:uint parmtype=bus_width:uint parmtype=input_cycle:uint parmtype=output_cycle:uint parmtype=erase_delay:uint parmtype=programm_delay:uint parmtype=access_delay:uint parmtype=fourth_id_byte:uint parmtype=third_id_byte:uint parmtype=second_id_byte:uint parmtype=first_id_byte:uint retpoline=Y srcversion=0D0006EFEC083D5DA056F88 depends=nand,nand_ids vermagic=2.6.32-754.35.1.el6.x86_64 SMP mod_unload modversions ( 8 @ H P ` h p x + 4 > ( I ( 0 8 0 @ S P X ` ` h x 8 < @ ( 0 @ H P X h p x
0 8 @ H X ` h $ x e ( 50 8 U@ H P X ` h p x X X
@#R module_layout _Wn kmem_cache_destroy 9O per_cpu__current_task \4Z __kmalloc h vmalloc ˑ malloc_sizes
ř param_set_ulong ) simple_strtoul fC param_array_get To filp_close __const_udelay = add_mtd_partitions -̒Q nand_release vfree Z,< sprintf 'wE param_array_set kstrdup C __list_add @4A param_get_charp vfs_read memset Jn random32 cs printk E nand_default_bbt write_inode_now find_or_create_page 9 mcount
)s kmem_cache_free m per_cpu__kernel_stack [D! list_del h unlock_page \ kmem_cache_alloc __stack_chk_fail param_get_uint
nand_scan \ɢ. __x86_indirect_thunk_rax lv param_get_ulong D kmem_cache_alloc_trace 9 kmem_cache_create ej param_set_charp z kfree dl# memcpy H̅2 param_set_uint r put_page rk nand_flash_ids L find_get_page k} __udelay a vfs_write Cq filp_open 2 ( 9 @ @ P ` @ P ` 0 0 @
@
0 0 0 8 0 @ @ H @ P P X P nandsim ` d module.sig ^ _
ǽq ǸNPHUՙ?aP=M!xr2n -GxS/]Z gٲ~l7@ޏ
" 0 . @ 9 P E H V o h n r 8 X ` P @ W ` l
, Z -
< F ' S % I e 0 w 0# % { $ ( 0 '
$ 1 0 ; @ F O s _ < c @ m | % 0 J ` B , D = Q L c v @ O A . @ % A / : ` > 3 , 6 D ; Z ` M r K W ] ( ( ( )
B W P ( g { @ x ( ` ( + ( " 4
8 P ( c > z ( I
@ ( S ` 0
h ( +
< ( H X @
o (
`
(
(
5 0 ( J
c
| X (
( ( %
> Z ( q @ ( ` (
%
@
H ( V
p
w
#
@
@
0
* 3 o B Q X ^ n
P ) ? O V P d x
)
4
D
S
c
p
x
nandsim.c free_device free_lists weak_blocks weak_pages grave_pages erase_block_wear ns_cleanup_module nsmtd ns_nand_read_word dbg get_state_name switch_to_ready_state update_wear total_wear rptwear_cnt rptwear wear_eb_count get_state_by_command find_operation ops ns_device_ready get_partition_name ns_init_module bus_width ns_hwcontrol ns_nand_read_byte ns_nand_write_buf ns_nand_read_buf ns_nand_verify_buf third_id_byte fourth_id_byte first_id_byte second_id_byte weakblocks weakpages gravepages overridesize parts_num parts cache_file badblocks get_pages read_file write_file bitflips do_state_action log do_delays programm_delay output_cycle access_delay input_cycle erase_delay switch_state ns_verify_buf __mod_description2364 __mod_author2363 __mod_license2362 __mod_cache_file161 __mod_overridesize160 __mod_rptwear157 __mod_gravepages156 __mod_bitflips153 __mod_weakpages152 __mod_weakblocks149 __mod_badblocks146 __mod_parts144 __mod_dbg143 __mod_log142 __mod_do_delays141 __mod_bus_width140 __mod_input_cycle139 __mod_output_cycle138 __mod_erase_delay137 __mod_programm_delay136 __mod_access_delay135 __mod_fourth_id_byte134 __mod_third_id_byte133 __mod_second_id_byte132 __mod_first_id_byte131 __mod_cache_filetype129 __param_cache_file __param_str_cache_file __mod_overridesizetype128 __param_overridesize __param_str_overridesize __mod_rptweartype127 __param_rptwear __param_str_rptwear __mod_gravepagestype126 __param_gravepages __param_str_gravepages __mod_bitflipstype125 __param_bitflips __param_str_bitflips __mod_weakpagestype124 __param_weakpages __param_str_weakpages __mod_weakblockstype123 __param_weakblocks __param_str_weakblocks __mod_badblockstype122 __param_badblocks __param_str_badblocks __mod_partstype121 __param_parts __param_str_parts __param_arr_parts __mod_dbgtype120 __param_dbg __param_str_dbg __mod_logtype119 __param_log __param_str_log __mod_do_delaystype118 __param_do_delays __param_str_do_delays __mod_bus_widthtype117 __param_bus_width __param_str_bus_width __mod_input_cycletype116 __param_input_cycle __param_str_input_cycle __mod_output_cycletype115 __param_output_cycle __param_str_output_cycle __mod_erase_delaytype114 __param_erase_delay __param_str_erase_delay __mod_programm_delaytype113 __param_programm_delay __param_str_programm_delay __mod_access_delaytype112 __param_access_delay __param_str_access_delay __mod_fourth_id_bytetype111 __param_fourth_id_byte __param_str_fourth_id_byte __mod_third_id_bytetype110 __param_third_id_byte __param_str_third_id_byte __mod_second_id_bytetype109 __param_second_id_byte __param_str_second_id_byte __mod_first_id_bytetype108 __param_first_id_byte __param_str_first_id_byte .LC140 nandsim.mod.c __mod_retpoline86 _rheldata __mod_srcversion77 __module_depends ____versions __mod_vermagic5 filp_open vfs_write __udelay __this_module find_get_page nand_flash_ids put_page cleanup_module param_set_uint memcpy kfree param_set_charp kmem_cache_create kmem_cache_alloc_trace param_get_ulong init_module __x86_indirect_thunk_rax nand_scan param_get_uint __stack_chk_fail kmem_cache_alloc do_bit_flips unlock_page list_del per_cpu__kernel_stack kmem_cache_free mcount do_read_error find_or_create_page write_inode_now nand_default_bbt printk random32 memset vfs_read param_get_charp __list_add kstrdup param_array_set sprintf vfree nand_release add_mtd_partitions __const_udelay filp_close param_array_get simple_strtoul param_set_ulong malloc_sizes vmalloc __kmalloc per_cpu__current_task kmem_cache_destroy nandsim.ko.debug ; .rodata.str1.1 .rodata.str1.8 .rela.data .rheldata .rela.rodata .symtab .strtab .shstrtab .rela__mcount_loc .note.gnu.build-id .rela__bug_table .rela.gnu.linkonce.this_module .note.module.sig .gnu_debuglink .rela__param .modinfo __versions .bss .rela.text .rela.init.text .rela.exit.text m @ $ p - . % (S o S T
a 9 `q ' 4 r ` 2 r e 2 M j ` ` ` p У @ ` [ * @ $ м ` 0 0 x A 8 H I
, Q D !