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H11UHSHHd Ht` D HHHuH[ÐH诙H All events must be distinct.
%s N/A TIMER timer %d
%*s %.*s unset cpu_type '%s' is not valid
%s:%lu:%lu:1:1
Using timer interrupt.
No events given.
%d %d
Too many arguments.
%d %s
No such event "%s"
Group %u : : (counter: %d , : (ext: %s : (counter: all )
(min count: %d) zero Unit masks (default %s)
Unit masks (default 0x%x)
----------
0x%.2x: (name= ) use the given CPU type check-events ignore-count get-cpu-type get-default-event get the default event callgraph use this callgraph depth show version xml list events as XML extra-mask print extra mask for event symbolic-unit-mask Help options: Invalid unit mask %x for event %s
No event named %s is available.
Invalid unit mask 0x%x for event %s
Count %d for event %s is below the minimum %d
Not enough hardware counters. Need %lu counters but only has %lu.
Couldn't allocate hardware counters for the selected events.
you should upgrade oprofile or force the use of timer mode
More than one event specified.
See BIOS and Kernel Developer's Guide for AMD Athlon and AMD Opteron Processors
(26094.pdf), Section 10.2
See BIOS and Kernel Developer's Guide for AMD Family 10h Processors
(31116.pdf), Section 3.14
See BIOS and Kernel Developer's Guide for AMD Family 11h Processors
(41256.pdf), Section 3.14
See BIOS and Kernel Developer's Guide for AMD Family 12h Processors
See BIOS and Kernel Developer's Guide for AMD Family 14h Processors
See BIOS and Kernel Developer's Guide for AMD Family 15h Processors
See BIOS and Kernel Developer's Guide for AMD Processors
See AMD Athlon Processor x86 Code Optimization Guide
(22007.pdf), Appendix D
See Intel Architecture Developer's Manual Volume 3B, Appendix A and
Intel Architecture Optimization Reference Manual
See Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 3B Chapter 18 for architectural perfmon events
This is a limited set of fallback events because oprofile doesn't know your CPU
See Intel Itanium Processor Reference Manual
for Software Development (Document 245320-003),
Intel Itanium Processor Reference Manual
for Software Optimization (Document 245473-003),
Intel Itanium 2 Processor Reference Manual
for Software Development and Optimization (Document 251110-001)
See Alpha Architecture Reference Manual
http://download.majix.org/dec/alpha_arch_ref.pdf
See Intel XScale Core Developer's Manual
Chapter 8 Performance Monitoring
See ARM11 MPCore Processor Technical Reference Manual r1p0
Page 3-70, performance counters
See ARM11 Technical Reference Manual
See Cortex-A8 Technical Reference Manual
Cortex A8 DDI (ARM DDI 0344B, revision r1p1)
See ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition
Scorpion Processor Family Programmer's Reference Manual (PRM)
See Cortex-A9 Technical Reference Manual
Cortex A9 DDI (ARM DDI 0388E, revision r2p0)
See Cortex-A5 Technical Reference Manual
Cortex A5 DDI (ARM DDI 0433B, revision r0p1)
See Cortex-A7 MPCore Technical Reference Manual
Cortex A7 DDI (ARM DDI 0464D, revision r0p3)
See Cortex-A15 MPCore Technical Reference Manual
Cortex A15 DDI (ARM DDI 0438F, revision r3p1)
See ARM Architecture Reference Manual
ARMv8, for ARMv8-A architecture profile
DDI (ARM DDI0487A.a)
See Cortex-A57 MPCore Technical Reference Manual
Cortex A57 DDI (ARM DDI 0488D, revision r1p1)
See Cortex-A53 MPCore Technical Reference Manual
Cortex A57 DDI (ARM DDI 0500D, revision r0p2)
See PA6T Power Implementation Features Book IV
Chapter 7 Performance Counters
When using operf, events may be specified without a '_GRP' suffix.
If _GRP (i.e., group number) is not specified, one will be automatically
selected for use by the profiler. OProfile post-processing tools will
always show real event names that include the group number suffix.
Documentation for IBM POWER7 can be obtained at:
http://www.power.org/events/Power7/
No public performance monitoring doc available for older processors.
This processor type is fully supported with operf; opcontrol timer mode may be available.
See Power ISA 2.07 at https://www.power.org/
Obtain Cell Broadband Engine documentation at:
http://www-306.ibm.com/chips/techlib/techlib.nsf/products/Cell_Broadband_Engine
See Programming the MIPS64 20Kc Processor Core User's manual available from www.mips.com
See Programming the MIPS32 24K Core available from www.mips.com
See Programming the MIPS64 25Kf Processor Core User's manual available from www.mips.com
See Programming the MIPS32 34K Core Family available from www.mips.com
See Programming the MIPS32 74K Core Family available from www.mips.com
See Programming the MIPS32 1004K Core Family available from www.mips.com
See Programming the MIPS64 5K Processor Core Family Software User's manual available from www.mips.com
See NEC R10000 / R12000 User's Manual
http://www.necelam.com/docs/files/U10278EJ3V0UM00.pdf
See RM7000 Family User Manual available from www.pmc-sierra.com
See RM9000x2 Family User Manual available from www.pmc-sierra.com
See NEC VR5443 User's Manual, Volume 1
http://www.necelam.com/docs/files/1375_V1.pdf
See NEC R10000 / R12000 User's Manual
http://www.necel.com/nesdis/image/U16677EJ3V0UM00.pdf
See loongson2 RISC Microprocessor Family Reference Manual
See PowerPC e500 Core Complex Reference Manual
Chapter 7: Performance Monitor
Downloadable from http://www.freescale.com
See PowerPC e300 Core Reference Manual
Downloadable from http://www.freescale.com
See MPC7450 RISC Microprocessor Family Reference Manual
Chapter 11: Performance Monitor
Downloadable from http://www.freescale.com
See AVR32 Architecture Manual
Chapter 6: Performance Counters
http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf
See Tilera development doc: Multicore Development Environment Optimization Guide.
Contact Tilera Corporation or visit http://www.tilera.com for more information.
IBM System z CPU Measurement Facility
http://www-01.ibm.com/support/docview.wss?uid=isg26fcd1cc32246f4c8852574ce0044734a
%d is not a valid processor type.
oprofile: available events for CPU type "%s"
For architectures using unit masks, you may be able to specify
unit masks by name. See 'opcontrol' or 'operf' man page for more details.
check the given event descriptions for validity do not validate count value (used by ocount) default unit mask for the given event show the auto-detected CPU type resolve an event with symbolic unit mask into numeric unit and extra masks '@ '@ '@ '@ &@ '@ @ '@ &@ &@ &@ &@ '@ &@ &@ &@ &@ &@ '@ &@ &@ &@ &@ &@ &@ &@ &@ &@ &@ &@ &@ &@ |&@ r&@ h&@ h&@ ^&@ T&@ T&@ '@ J&@ '@ &@ &@ @&@ 6&@ ,&@ "&@ &@ &@ &@ &@ %@ %@ %@ &@ &@ '@ '@ %@ '@ %@ %@ %@ %@ %@ %@ '@ %@ %@ '@ %@ %@ %@ x%@ x%@ '@ n%@ d%@ Z%@ '@ x%@ P%@ -%@ -%@ '@ '@ #%@ %@ &@ '@ '@ '@ oprofile: parse error in %s, line %u
oprofile: could not find unit mask %s
next_token(): garbage at end of line oprofile: could not open event description file %s
combined unit mask must be all the same types combined unit mask must be all bitmasks or exclusive too many members in combined unit mask Default unit mask not supported for this event.
Please speicfy a unit mask by name, using the first word of the unit mask description
Unit mask (0x%x) is non unique.
Please specify the unit mask using the first word of the description
Cannot find unit mask %s for %s
Named unit mask (%s) not allowed for event without 'extra:' values.
Please specify the numerical value for the unit mask. See 'opcontrol'
or 'operf' man page for more info.
Unit mask name `%s' not unique. Please use a numerical unit mask
oprofile: could not open event mapping file %s
expected long hexadecimal value Error: Missing information in line %d of event mapping file %s
oprofile: could not open unit mask description file %s
mandatory um %s doesn't contain exactly one entry (%s)
um %s default mask is not valid (%s)
exclusive um %s default value is not valid (%s)
Error: TIMER event cannot be redefined.
Error: Event %s uses TIMER which is reserverd for timer based sampling.
Error: timer_unit_mask unit mask cannot be redefined.
Ambiguous bitmask: Unit mask values cannot include non-unique numerical values (i.e., 0x%x).
Use ophelp to see the unit mask values for event %s.
CPU_CLK_UNHALTED cpu_clk_unhalted RTC_INTERRUPTS GLOBAL_POWER_EVENTS CPU_CYCLES INSTRUCTIONS INSTRUCTIONS_GRADUATED INSTRUCTIONS_ISSUED INSN_SURVIVED_STAGE7 INSTRUCTIONS_EXECUTED CPU_CLK HWSAMPLING OPROFILE_EVENTS_DIR /usr/share/oprofile/ %s/%s/%s 0x%x 0X%x expected hexadecimal value expected decimal value next_token() expected ':' desc GenuineIntel duplicate name: tag invalid event name duplicate event: tag counters duplicate counters: tag cpuid ext duplicate ext: tag duplicate um: tag Empty unit mask minimum duplicate minimum: tag filter include tags before include: non whitespace after include: unknown tag Cannot find event %s
duplicate event tag mmcr0 duplicate mmcr0 tag mmcr1 duplicate mmcr1: tag %Lx mmcra duplicate mmcra: tag mmcr0:%u mmcr1:%Lu mmcra:%u edge inv cmask=%x%n any pebs Illegal extra field modifier parse_um() expected :value include must be on its own duplicate type: tag mandatory bitmask exclusive invalid unit mask type default duplicate default: tag 0x invalid unit mask tag Missing name for unit mask Missing type for unit mask no unit mask name line extra: invalid unit mask entry unit_masks um %s is not used
timer_unit_mask No unit mask Timer based sampling X)@ X)@ X)@ X)@ (@ h)@ )@ )@ )@ )@ X)@ )@ (@ (@ (@ (@ (@ X)@ )@ )@ (@ (@ (@ (@ (@ (@ (@ (@ (@ )@ )@ )@ )@ ()@ 8)@ 8)@ H)@ H)@ X)@ (@ X)@ (@ (@ (@ X)@ (@ )@ )@ (@ H)@ )@ )@ X)@ X)@ (@ (@ X)@ X)@ X)@ X)@ )@ (@ (@ X)@ X)@ X)@ X)@ )@ )@ X)@ (@ (@ (@ )@ )@ X)@ )@ )@ )@ X)@ )@ X)@ (@ (@ X)@ X)@ )@ )@ )@ )@ )@ Invalid event part %s
Invalid event %s
Invalid count for event %s
Too many events specified: CPU only has %lu counters.
TIMER event cannot be used in combination with hardware counters.
invalid cpu type /dev/oprofile/timer Cannot open /proc/self/auxv Error close failed /proc/cpuinfo Unable to open /proc/cpuinfo
/dev/oprofile/cpu_type uname failed x86_64 i?86 i386/ppro i386/pii i386/piii i386/p6_mobile siblings i386/p4 i386/p4-ht AuthenticAMD x86-64/hammer x86-64/family10 x86-64/family%xh x86-64/generic ppc64 cpu ppc64/ arm aarch64 CPU implementer CPU part Unable to parse CPU part %s
arm/armv6 arm/mpcore arm/armv7-ca5 arm/armv7-ca7 arm/armv7 arm/armv7-ca9 arm/armv7-ca15 arm/armv8-ca57 arm/armv8-ca53 arm/armv8-xgene arm/xscale1 arm/xscale2 tile model name tile/ mips cpu model Could not read cpu type.
Pentium Pro PII PIII Athlon i386/athlon CPU with timer interrupt CPU with RTC device rtc P4 / Xeon IA64 ia64/ia64 Itanium ia64/itanium Itanium 2 ia64/itanium2 AMD64 processors Alpha EV4 alpha/ev4 Alpha EV5 alpha/ev5 Alpha PCA56 alpha/pca56 Alpha EV6 alpha/ev6 Alpha EV67 alpha/ev67 Pentium M (P6 core) ARM/XScale PMU1 ARM/XScale PMU2 ppc64 POWER4 ppc64/power4 ppc64 POWER5 ppc64/power5 ppc64 POWER5+ ppc64/power5+ ppc64 970 ppc64/970 MIPS 20K mips/20K MIPS 24K mips/24K MIPS 25K mips/25K MIPS 34K mips/34K MIPS 5K mips/5K MIPS R10000 mips/r10000 MIPS R12000 mips/r12000 QED RM7000 mips/rm7000 PMC-Sierra RM9000 mips/rm9000 Sibyte SB1 mips/sb1 NEC VR5432 mips/vr5432 NEC VR5500 mips/vr5500 ppc/e500 ppc/e500v2 Core Solo / Duo i386/core PowerPC G4 ppc/7450 Core 2 i386/core_2 ppc64 POWER6 ppc64/power6 ppc64 970MP ppc64/970MP ppc64 Cell Broadband Engine ppc64/cell-be AMD64 family10 ppc64 PA6T ppc64/pa6t ARM 11MPCore ARM V6 PMU ppc64 POWER5++ ppc64/power5++ ppc/e300 AVR32 avr32 ARM Cortex-A8 Intel Architectural Perfmon i386/arch_perfmon AMD64 family11h x86-64/family11h ppc64 POWER7 ppc64/power7 ppc64 compat version 1 ppc64/ibm-compat-v1 Intel Core/i7 i386/core_i7 Intel Atom i386/atom Loongson2 mips/loongson2 i386/nehalem ARM Cortex-A9 MIPS 74K mips/74K MIPS 1004K mips/1004K AMD64 family12h x86-64/family12h AMD64 family14h x86-64/family14h AMD64 family15h x86-64/family15h i386/westmere ARMv7 Scorpion arm/armv7-scorpion ARMv7 ScorpionMP arm/armv7-scorpionmp i386/sandybridge TILE64 tile/tile64 TILEPro tile/tilepro TILE-GX tile/tilegx IBM System z10 s390/z10 IBM zEnterprise z196 s390/z196 i386/ivybridge ARM Cortex-A5 ARM Cortex-A7 ARM Cortex-A15 i386/haswell IBM zEnterprise EC12 s390/zEC12 AMD64 generic ppc64/architected_events_v1 ppc64 POWER8 ppc64/power8 i386/silvermont i386/broadwell APM X-Gene ARM Cortex-A57 ARM Cortex-A53 i386/skylake i386/goldmont MIPS 5Kc MIPS 20Kc MIPS 24Kc MIPS 25Kc MIPS 34Kc MIPS 74Kc MIPS M14Kc mips/M14Kc R14000 ICT Loongson-2 Assuming native platform profiling is supported.
Allocation of space for auxv failed. Error /proc/self/auxv read failed Recoverable error. Continuing.
Did not find processor type in /proc/cpuinfo.
/proc/sys/dev/oprofile/cpu_type NULL returned for one or both of AT_PLATFORM/AT_BASE_PLATFORM
AT_PLATFORM: %s; AT_BASE_PLATFORM: %s
Unable to parse CPU implementer %s
Unable to open cpu_type file for reading
Make sure you have done opcontrol --init
P4 / Xeon with 2 hyper-threads Intel Nehalem microarchitecture Intel Westmere microarchitecture Intel Sandy Bridge microarchitecture Intel Ivy Bridge microarchitecture Intel Haswell microarchitecture IBM Power Architected Events V1 Intel Silvermont microarchitecture Intel Broadwell microarchitecture Intel Skylake microarchitecture Intel Goldmont microarchitecture \@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ \@ \@ 8Z@ 8Z@ \@ 8Z@ \@ \@ \@ \@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ \@ 8Z@ 8Z@ 8Z@ 8Z@ \@ 8Z@ \@ \@ \@ \@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ \@ 8Z@ 8Z@ \@ 8Z@ \@ \@ \@ \@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ \@ \@ \@ 8Z@ 8Z@ 8Z@ 8Z@ \@ \@ \@ \@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ \@ \@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ \@ 8Z@ \@ \@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ \@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ 8Z@ \@ `@ `@ `@ `@ `@ `@ _@ _@ _@ _@ _@ _@ \@ _@ &@ c@ 2@ m@ 6@ v@ ;@ B@ N@ Ҩ@ g@ {@ @ @ @ @ @ @ @ @ ū@ @
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<%s%s NONE processor cputype title schemaversion mhz timersetup rtcinterrupts eventsetup eventname unitmask setupcount separatedcpus options session debuginfo excludedependent excludesymbols imagepath includesymbols merge classes class process pid thread tid binary module callers callees symbol idref self detaillo detailhi symboltable symboldata startingaddr codelength summarydata sampledata detailtable symboldetails detaildata vmaoffset bytestable bytes help_events header doc event_name group counter_mask min_count category init_xml_str_attr: snprintf failed
init_xml_dbl_attr: snprintf failed
init_xml_int_attr: snprintf failed
close_xml_element: snprintf failed
open_xml_element: snprintf failed
%lu oprofiled:op_close_file: op_read_int_from_file: Failed to open %s, reason %s
op_read_int_from_file: Failed to convert contents of file %s to integer
op_read_long_from_file: Failed to open %s, reason %s
op_read_long_from_file: Failed to convert contents of file %s to unsigned long
oprofiled:op_do_open_file: %s: %s oprofiled:op_write_file: wrote less than expected: %lu bytes.
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